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ST72344S4 bảng dữ liệu(PDF) 97 Page - STMicroelectronics

tên linh kiện ST72344S4
Giải thích chi tiết về linh kiện  SCI asynchronous serial interface
PDF  247 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72344S4 bảng dữ liệu(HTML) 97 Page - STMicroelectronics

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ST72344xx, ST2345xx
On-chip peripherals
Doc ID 12321 Rev 6
97/247
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus, the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 44.
Counter timing diagram, internal clock divided by 2
Figure 45.
Counter timing diagram, internal clock divided by 4
Figure 46.
Counter timing diagram, internal clock divided by 8
Note:
The device is in reset state when the internal reset signal is high. When it is low, the Device
is running.
CPU CLOCK
FFFD FFFE FFFF 0000
0001
0002
0003
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFC
FFFD
0000
0001
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFC
FFFD
0000



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