ST72344S4 datasheet(90/247 Pages) STMICROELECTRONICS

90 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

90/247

Doc ID 12321 Rev 6

11.2.7

MCC control/status register (MCCSR)

Reset value: 0000 0000 (00h)

Bit 7 = MCO Main clock out selection

This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by

software.

0: MCO alternate function disabled (I/O pin free for general-purpose I/O)

1: MCO alternate function enabled (fCPU on I/O port)

Note:

To reduce power consumption, the MCO function is not active in Active-halt mode.

Bits 6:5 = CP[1:0] CPU clock prescaler

These bits select the CPU clock prescaler which is applied in the different slow modes.

Their action is conditioned by the setting of the SMS bit. These two bits are set and

cleared by software.

Bit 4 = SMS Slow mode select

This bit is set and cleared by software.

0: Normal mode. fCPU = fOSC2

1: Slow mode. fCPU is given by CP1, CP0

See Section 9.2: Slow mode and Section 11.1: Window watchdog (WWDG) for more

details.

Bits 3:2 = TB[1:0] Time base control

These bits select the programmable divider time base. They are set and cleared by

software.

MCO

CP1

CP0

SMS

TB1

TB0

OIE

OIF

Read/Write

Table 41.

CPU clock prescaler selection

fCPU in Slow mode

CP1

CP0

fOSC2 / 2

fOSC2 / 4

fOSC2 / 8

fOSC2 / 16

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