ST72344S4 datasheet(87/247 Pages) STMICROELECTRONICS

87 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

87/247

11.1.7

Hardware watchdog option

If hardware watchdog is selected by option byte, the watchdog is always active and the

WDGA bit in the WDGCR is not used. Refer to the Option Byte description.

11.1.8

Using Halt mode with the WDG (WDGHALT option)

The following recommendation applies if Halt mode is used when the watchdog is enabled.

●

Before executing the HALT instruction, refresh the WDG counter, to avoid an

unexpected WDG reset immediately after waking up the microcontroller.

11.1.9

Interrupts

None.

11.1.10

Control register (WDGCR)

Reset value: 0111 1111 (7Fh)

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by hardware after a reset. When WDGA = 1,

the watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Note:

This bit is not used if the hardware watchdog option is enabled by option byte.

Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).

These bits contain the value of the watchdog counter. It is decremented every

16384 fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh

(T6 becomes cleared).

Window register (WDGWR)

Reset value: 0111 1111 (7Fh)

Bit 7 = Reserved

Bits 6:0 = W[6:0] 7-bit window value

These bits contain the window value to be compared to the downcounter.

WDGA

Read/Write

W6W5

W4W3

Read/Write

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