ST72344S4 datasheet(91/247 Pages) STMICROELECTRONICS

91 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

91/247

A modification of the time base is taken into account at the end of the current period

(previously set) to avoid an unwanted time shift. This allows to use this time base as a real-

time clock.

Bit 1 = OIE Oscillator interrupt enable

This bit set and cleared by software.

0: Oscillator interrupt disabled

1: Oscillator interrupt enabled

This interrupt can be used to exit from Active-halt mode.

When this bit is set, calling the ST7 software HALT instruction enters the Active-halt

power-saving mode.

Bit 0 = OIF Oscillator interrupt flag

This bit is set by hardware and cleared by software reading the MCCSR register. It

indicates when set that the main oscillator has reached the selected elapsed time

(TB1:0).

0: Timeout not reached

1: Timeout reached

Caution:

The BRES and BSET instructions must not be used on the MCCSR register to avoid

unintentionally clearing the OIF bit.

MCC beep control register (MCCBCR)

Reset value: 0000 0000 (00h)

Bits 7:2 = Reserved, must be kept cleared.

Bits 1:0 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.

Table 42.

Time base control

Counter

prescaler

Time base

TB1

TB0

fOSC2 = 4 MHz

fOSC2 = 8 MHz

16000

4 ms

2 ms

32000

8 ms

4 ms

80000

20 ms

10 ms

200000

50 ms

25 ms

000

BC1

BC0

Read/Write

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