ST72344S4 datasheet(67/247 Pages) STMICROELECTRONICS

67 / 247 page

ST72344xx, ST2345xx

Power-saving modes

Doc ID 12321 Rev 6

67/247

system is enabled, can generate a Watchdog reset (see Section 11.1: Window watchdog

(WWDG) for more details).

Figure 28.

Halt timing overview

Figure 29.

Halt mode flowchart

Note:

WDGHALT is an option bit. See Section 15.1: Option bytes for more details.

Peripheral clocked with an external clock source can still be active.

Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt).

Refer to Table 17: Interrupt mapping for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the

CC register are set to the current software priority level of the interrupt routine and

recovered when the CC register is popped.

Halt

Run

256 OR 4096 CPU

cycle delay

Reset

interrupt

Halt

instruction

Fetch

vector

[MCCSR.OIE=0]

RESET

INTERRUPT 3)

CPU

OSCILLATOR

PERIPHERALS 2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

XX 4)

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX 4)

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT 1)

WATCHDOG

RESET

CYCLE

HALT INSTRUCTION

(MCCSR.OIE=0)

(AWUCSR.AWUEN=0)

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