ST7MC1K2 datasheet(176/371 Pages) STMICROELECTRONICS

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10.5.11

LIN divider (LDIV) registers

LDIV is coded using the two registers LPR and LPFR. In LIN slave mode, the LPR register is

accessible at the address of the SCIBRR register and the LPFR register is accessible at the

address of the SCIETPR register.

LIN prescaler register (LPR)

Caution:

LPR and LPFR registers have different meanings when reading or writing to them.

Consequently bit manipulation instructions (BRES or BSET) should never be used to modify

the LPR[7:0] bits, or the LPFR[3:0] bits.

LIN prescaler fraction register (LPFR)

LPR

Reset value: 0000 0000 (00h)

654

LPR[7:0]

R/W

Table 72.

LPR register description

Bit

Name

Function

7:0 LPR[7:0]

LIN prescaler (mantissa of LDIV)

These 8 bits define the value of the mantissa of the LDIV (see Table 73).

Table 73.

LIN mantissa rounded values

LPR[7:0]

Rounded mantissa (LDIV)

00h

SCI clock disabled

01h

FEh

254

FFh

255

LPFR

Reset value: 0000 0000 (00h)

654

Reserved

LPFR[3:0]

-R/W

Table 74.

LPFR register description

Bit

Name

Function

7:4

Reserved

3:0 LPFR[3:0]

Fraction of LDIV

These 4 bits define the fraction of the LDIV (see Table 75).

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