ST7MC1K2 datasheet(58/371 Pages) STMICROELECTRONICS

58 / 371 page

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Supply, reset and clock management

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto,

58/371

6.6.8

MCC beep control register (MCCBCR)

6.6.9

Main clock controller register map and reset values

MCCBCR

Reset value: 0000 0000 (00h)

76543

210

Reserved

ADSTS

ADC IE

BC[1:0]

R/W

Table 14.

MCCBCR register description

Bit

Name

Function

7:4

Reserved, must be kept cleared

3ADSTS

A/D converter sample time stretch

This bit is set and cleared by software to enable or disable the A/D converter sample time stretch

feature.

0: AD sample time stretch disabled (for standard impedance analog inputs)

1: AD sample time stretch enabled (for high impedance analog inputs)

2ADC IE

A/D converter interrupt enable

This bit is set and cleared by software to enable or disable the A/D converter interrupt.

0: AD Interrupt disabled

1: AD Interrupt enabled

1:0

BC[1:0]

Beep control

These 2 bits select the PF1 pin beep capability:

00: Beep mode (with fOSC2 =8 MHz) =off

01: Beep mode (with fOSC2 = 8 MHz) = .~2 kHz (output beep signal ~50% duty

cycle)

10: Beep mode (with fOSC2 = 8 MHz) = .~1 kHz (output beep signal ~50% duty

cycle)

11: Beep mode (with fOSC2 = 8 MHz) = .~500 Hz (output beep signal ~50% duty

cycle)

The beep output signal is available in Active Halt mode but has to be disabled to reduce the

consumption.

Table 15.

Main clock controller register map and reset values

Address (Hex.)

0040h

SICSR, page0

reset value

PAGE

VDIE

VDF

LVDRF

CFIE

CSSD

WDGRF

0040h

SICSR, page1

reset value

PAGE

VCOEN

LOCK

PLLEN

CKSEL

002Ch

MCCSR

reset value

MCO

CP1

CP0

SMS

TB1

TB0

OIE

OIF

002Dh

MCCBCR

reset value

ADSTS

ADCIE

BC1

BC0

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