ST7MC1K2 datasheet(83/371 Pages) STMICROELECTRONICS

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I/O ports

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9.5

Interrupts

The external interrupt event generates an interrupt if the corresponding configuration is

selected with DDR and OR registers and the interrupt mask in the CC register is not active

(RIM instruction).

9.5.1

I/O port implementation

The I/O port register configurations are summarized below.

Standard ports

Interrupt ports

Table 28.

I/O port interrupt control/wake-up capability

Interrupt event

Event flag Enable control bit Exit from WAIT Exit from HALT

External interrupt on selected

external event

DDRx, ORx

Yes

Table 29.

Standard ports: PA4, PA2:0, PB5:0, PC7:4, PD7:6, PE5:0, PF5:0, PG7:0,

PH7:0

Mode

DDR

Floating input

Pull-up input

Open drain output

Push-pull output

Table 30.

Interrupt ports with pull-up: PA6, PA3, PB6, PC3, PC1, PD5, PD4, PD2

Mode

DDR

Floating input

Pull-up interrupt input

Open drain output

Push-pull output

Table 31.

Interrupt ports without pull-up: PA7, PA5, PB7, PC2, PC0, PD6, PD3, PD

Mode

DDR

Floating input

Floating interrupt input

Open drain output

Push-pull output

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