ST7MC1K2 datasheet(95/371 Pages) STMICROELECTRONICS

95 / 371 page

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ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

On-chip peripherals

95/371

Figure 35.

Output compare control

Independent PWM signal generation

This mode allows up to four pulse width modulated signals to be generated on the PWMx output pins with

minimum core processing overhead. This function is stopped during Halt mode.

Each PWMx output signal can be selected independently using the corresponding OEx bit in the PWM

Control register (PWMCR). When this bit is set, the corresponding I/O pin is configured as output push-

pull alternate function.

The PWM signals all have the same frequency which is controlled by the counter period and the ARTARR

fPWM =fCOUNTER/(256 - ARTARR)

When a counter overflow occurs, the PWMx pin level is changed depending on the corresponding OPx

(output polarity) bit in the PWMCR register. When the counter reaches the value contained in one of the

output compare register (OCRx) the corresponding PWMx pin level is restored.

It should be noted that the reload values also affect the value and the resolution of the duty cycle of the

PWM output signal. To obtain a signal on a PWMx pin, the contents of the OCRx register must be greater

than the contents of the ARTARR register.

The maximum available resolution for the PWMx duty cycle is:

Resolution = 1/(256 - ARTARR)

Note:

To get the maximum resolution (1/256), the ARTARR register must be 0. With this maximum

resolution, 0% and 100% can be obtained by changing the polarity.

Counter

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

ARTARR = FDh

fCOUNTER

OCRx

PWMDCRx

FDh

FEh

FDh

FEh

FFh

PWMx

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Product(s)

- Obsolete

Product(s)

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