ST7MC1K2 datasheet(135/371 Pages) STMICROELECTRONICS

135 / 371 page

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On-chip peripherals

135/371

Figure 60.

Single master/multiple slave configuration

10.4.6

Low power modes

Using the SPI to wake up the device from Halt mode

In slave configuration, the SPI is able to wake up the device from Halt mode through a SPIF

interrupt. The data received is subsequently read from the SPIDR register when the

software is running (interrupt vector fetch). If multiple data transfers have been performed

before software clears the SPIF bit, then the OVR bit is set by hardware.

Note:

When waking up from Halt mode, if the SPI remains in slave mode, it is recommended to

perform an extra communications cycle to bring the SPI from Halt mode state to normal

state. If the SPI exits from slave mode, it returns to normal state immediately.

Caution:

The SPI can wake up the device from Halt mode only if the slave select signal (external SS

pin or the SSI bit in the SPICSR register) is low when the device enters Halt mode. So, if

slave selection is configured as external (see Slave select management on page 129), make

sure the master drives a low level on the SS pin when the slave enters Halt mode.

MOSI

MISO

SCK

Slave device

SCK

Slave device

SCK

Slave device

MOSI

MISO

MOSI

MISO

MOSI

MISO

MOSI

MISO

SCK

Master

device

Table 54.

Effect of low power modes on SPI

Mode

Description

Wait

No effect on SPI.

SPI interrupt events cause the device to exit from Wait mode.

Halt

SPI registers are frozen.

In Halt mode, the SPI is inactive. SPI operation resumes when the device is

woken up by an interrupt with ‘exit from Halt mode’ capability. The data received

is subsequently read from the SPIDR register when the software is running

(interrupt vector fetching). If several data are received before the wake-up event,

then an overrun error is generated. This error can be detected after the fetch of

the interrupt routine that woke up the device.

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