SPC564A80L7 datasheet(115/157 Pages) STMICROELECTRONICS

115 / 157 page

SPC564A74L7, SPC564A80B4, SPC564A80L7

Electrical characteristics

Doc ID 15399 Rev 9

115/157

3.17.2

IEEE 1149.1 interface timing

Note:

The Nexus/JTAG Read/Write Access Control/Status Register (RWCS) write (to begin a read

access) or the write to the Read/Write Access Data Register (RWD) (to begin a write

access) does not actually begin its action until 1 JTAG clock (TCK) after leaving the JTAG

Update-DR state. This prevents the access from being performed and therefore will not

signal its completion via the READY (RDY) output unless the JTAG controller receives an

additional TCK. In addition, EVTI is not latched into the device unless there are clock

transitions on TCK.

The tool/debugger must provide at least one TCK clock for the EVTI signal to be recognized

by the MCU. When using the RDY signal to indicate the end of a Nexus read/write access,

ensure that TCK continues to run for at least 1 TCK after leaving the Update-DR state. This

can be just a TCK with TMS low while in the Run-Test/Idle state or by continuing with the

Table 38.

JTAG pin AC electrical characteristics(1)

Symbol

Characteristic

Min.

Value

Max.

Value

Unit

1tJCYC

TCK Cycle Time

100

—

2tJDC

TCK Clock Pulse Width

3tTCKRISE

TCK Rise and Fall Times (40% -

70%)

—3

4tTMSS, tTDIS

TMS, TDI Data Setup Time

—

5tTMSH, tTDIH

TMS, TDI Data Hold Time

—

6tTDOV

TCK Low to TDO Data Valid

—

22(2)

7tTDOI

TCK Low to TDO Data Invalid

—

8tTDOHZ

TCK Low to TDO High Impedance

—

9tJCMPPW

JCOMP Assertion Time

100

—

tJCMPS

JCOMP Setup Time to TCK Low

—

tBSDV

TCK Falling Edge to Output Valid

—

tBSDVZ

TCK Falling Edge to Output Valid out

of High Impedance

—50

tBSDHZ

TCK Falling Edge to Output High

Impedance

—50

tBSDST

Boundary Scan Input Valid to TCK

Rising Edge

25(3)

—ns

tBSDHT

TCK Rising Edge to Boundary Scan

Input Invalid

25(3)

—ns

JTAG timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V with multi-voltage pads programmed to Low-

Swing mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b11. These specifications apply to JTAG boundary

scan only. See Table 39 for functional specifications.

Pad delay is 8–10 ns. Remainder includes TCK pad delay, clock tree delay logic delay and TDO output pad delay.

For 20 MHz TCK.

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