DS2196 datasheet(38/157 Pages) DALLAS

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DS2196

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Table 6-3: TPOSB/TNEGB Data Source Select

TTDSS1 TTDSS0

Data Source

Pass tpos/tclk/tneg from the framer through to the

TPOSOB/TCLKOB/TNEGOB pins.

Force TPOSOB to source data from the BERT circuit. TNEGOB

is the frame sync pulse.

Force TPOSOB high. TNEGOB is the frame sync pulse.

Force TPOSOB and TNEGOB high.

Payload Loopback A

Payload Loopback When CCR1A.1 is set to a 1, the Framer/Formatter A will be forced into Payload

Loopback (PLB). Normally, this loopback is only enabled when ESF framing is being performed but can

be enabled also in D4 framing applications. In a PLB situation, the DS2196 will loop the 192 bits of

payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS

framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the

DS2196. When PLB is enabled, the following will occur:

1. The TCLKOA signal will become synchronous with RCLKA instead of TCLKA.

2. Data will be transmitted from the TRING and TTIP pins synchronous with RCLKA instead of

TCLKA.

3. All of the receive side signals will continue to operate normally.

4. The TCHCLKA and TCHBLKA signals are forced low.

5. TX serial data into Formatter A is ignored.

Payload Loopback B

When CCR1B.1 is set to a 1, the Framer/Formatter B will be forced into Payload Loopback (PLB).

Normally, this loopback is only enabled when ESF framing is being performed but can be enabled also in

D4 framing applications. In a PLB situation, the DS2196 will loop the 192 bits of payload data (with

BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6

calculation, and the FDL bits are not looped back, they are reinserted by the DS2196. When PLB is

enabled, the following will occur:

1. The TCLKOB signal will become synchronous with RCLKIB instead of TCLKB.

2. Data will be transmitted from the TPOSOB and TNEGOB pins synchronous with RCLKIB instead of

TCLKB.

3. All of the receive side signals will continue to operate normally.

4. The TCHCLKB and TCHBLKB signals are forced low.

5. TX serial data into Formatter B is ignored.

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