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DS2196 bảng dữ liệu(PDF) 81 Page - Dallas Semiconductor

tên linh kiện DS2196
Giải thích chi tiết về linh kiện  T1 Dual Framer LIU
PDF  157 Pages
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nhà sản xuất  DALLAS [Dallas Semiconductor]
Trang chủ  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS2196 bảng dữ liệu(HTML) 81 Page - Dallas Semiconductor

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RDNCD2A: RECEIVE DOWN CODE DEFINITION REGISTER 2 FRAMER A
(Address = 18 Hex)
RDNCD2B: RECEIVE DOWN CODE DEFINITION REGISTER 2 FRAMER B
(Address = B8 Hex)
(MSB)
(LSB)
C7
C6
C5
C4
C3
C2
C1
C0
SYMBOL
POSITION
NAME AND DESCRIPTION
C7
RDNCD2.7
Receive Down Code Definition Bit 7. A Don’t Care if a 1 to
7 bit length is selected.
C6
RDNCD2.6
Receive Down Code Definition Bit 6. A Don’t Care if a 1 to
7 bit length is selected.
C5
RDNCD2.5
Receive Down Code Definition Bit 5. A Don’t Care if a 1 to
7 bit length is selected.
C4
RDNCD2.4
Receive Down Code Definition Bit 4. A Don’t Care if a 1 to
7 bit length is selected.
C3
RDNCD2.3
Receive Down Code Definition Bit 3. A Don’t Care if a 1 to
7 bit length is selected.
C2
RDNCD2.2
Receive Down Code Definition Bit 2. A Don’t Care if a 1 to
7 bit length is selected.
C1
RDNCD2.1
Receive Down Code Definition Bit 1. A Don’t Care if a 1 to
7 bit length is selected.
C0
RDNCD2.0
Receive Down Code Definition Bit 0. A Don’t Care if a 1 to
7 bit length is selected.
RSCCA: IN–BAND RECEIVE SPARE CONTROL REGISTER FRAMER A
(Address = 1D Hex)
RSCCB: IN–BAND RECEIVE SPARE CONTROL REGISTER FRAMER B
(Address = BD Hex)
(MSB)
(LSB)
–––––
RSC2
RSC1
RSC0
SYMBOL
POSITION
NAME AND DESCRIPTION
–
RSCC.7
Not Assigned. Should be set to 0 when written to.
–
RSCC.6
Not Assigned. Should be set to 0 when written to.
–
RSCC.5
Not Assigned. Should be set to 0 when written to.
–
RSCC.4
Not Assigned. Should be set to 0 when written to.
–
RSCC.3
Not Assigned. Should be set to 0 when written to.
RSC2
RSCC.2
Receive Spare Code Length Definition Bit 2. See Table 12–2
RSC1
RSCC.1
Receive Spare Code Length Definition Bit 1. See Table 12–2
RSC0
RSCC.0
Receive Spare Code Length Definition Bit 0. See Table 12–2



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