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LAN9250 bảng dữ liệu(PDF) 145 Page - Microchip Technology

tên linh kiện LAN9250
Giải thích chi tiết về linh kiện  Integrated Ethernet PHY with HP Auto-MDIX
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 2015 Microchip Technology Inc.
DS00001913A-page 145
LAN9250
11.6.2
BROADCAST DETECTION
Setting the Broadcast Wakeup Enable (BCST_EN) bit in the Host MAC Wake-up Control and Status Register
(HMAC_WUCSR) places the MAC in the Broadcast detection mode. In this mode, normal data reception is disabled,
and detection logic within the MAC examines the destination address of each received frame.
When a frame whose destination address is FF FF FF FF FF FF is received, the Broadcast Frame Received
(BCAST_FR) bit in the WUCSR is set. When the host clears the BCST_EN bit, the Host MAC will resume normal receive
operation.
11.6.3
WAKE-UP FRAME DETECTION
Eight programmable wakeup frame filters are supported. Each filter has a 128-bit byte mask that indicates which bytes
of the frame should be compared by the MAC. A CRC-16 is calculated over these bytes. The result is then compared
with the filter’s respective CRC-16 to determine if a match exists.
Setting the Wake-Up Frame Enable (WUEN) in the Host MAC Wake-up Control and Status Register (HMAC_WUCSR),
places the Host MAC in the wake-up frame detection mode. In this mode, normal data reception is disabled, and detec-
tion logic within the Host MAC examines received data for the pre-programmed wake-up frame patterns.
Upon detection, the Remote Wake-Up Frame Received (WUFR) in the Host MAC Wake-up Control and Status Register
(HMAC_WUCSR) register is set. When the host clears the WUEN bit, the Host MAC will resume normal receive oper-
ation.
Before putting the Host MAC into the wake-up frame detection state, the host must provide the detection logic with a list
of sample frames and their corresponding byte masks. This information must be written into the Host MAC Wake-up
Frame Filter Register (HMAC_WUFF). The wake-up frame filter is configured through this register using an index mech-
anism. After power-on reset, hardware reset, or soft reset, the Host MAC loads the first value written to the
HMAC_WUFF register to the first DWORD in the wake-up frame filter (filter 0 byte mask 0). The second value written
to this register is loaded to the second DWORD in the wake-up frame filter (filter 0 byte mask 1) and so on for all 40
DWORDs. The wake-up frame filter functionally is described below.
The Host MAC supports eight programmable 128-bit wake-up filters that support many different receive packet patterns.
If remote wake-up mode is enabled, the remote wake-up function receives all frames addressed to the Host MAC. It
then checks each frame against the enabled filter and recognizes the frame as a remote wake-up frame if it passes the
wakeup frame filter register’s address filtering and CRC value match.
In order to determine which bytes of the frames should be checked by the CRC module, the Host MAC uses a program-
mable byte mask and a programmable pattern offset for each of the eight supported filters.
The pattern’s offset defines the location of the first byte that should be checked in the frame. Since the destination
address is checked by the address filtering function, the pattern offset is always greater than 12.
The byte mask is a 128-bit field that specifies whether or not each of the 128 contiguous bytes within the frame, begin-
ning in the pattern offset, should be checked. If bit j in the byte mask is set, the detection logic checks byte offset +j in
the frame. In order to load the wake-up frame filter, the host must perform 40 writes to the Host MAC Wake-up Frame
Filter Register (HMAC_WUFF). The contents of the Host MAC Wake-up Frame Filter Register (HMAC_WUFF) may be
obtained by reading all 40 DWORDs. Table 11-2 shows the wake-up frame filter register’s structure.
At the completion of the CRC-16 checking process, the CRC-16 calculated using the pattern offset and byte mask is
compared to the expected CRC-16 value associated with the filter. If a match occurs, a remote wakeup event is sig-
naled.
TABLE 11-2:
WAKEUP FRAME FILTER REGISTER STRUCTURE
Filter 0 Byte Mask 0
Filter 0 Byte Mask 1
Filter 0 Byte Mask 2
Filter 0 Byte Mask 3
Filter 1 Byte Mask 0
Filter 1 Byte Mask 1



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