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LAN9250 bảng dữ liệu(PDF) 248 Page - Microchip Technology

tên linh kiện LAN9250
Giải thích chi tiết về linh kiện  Integrated Ethernet PHY with HP Auto-MDIX
PDF  421 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9250 bảng dữ liệu(HTML) 248 Page - Microchip Technology

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LAN9250
DS00001913A-page 248
 2015 Microchip Technology Inc.
Note 10:
Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg-
ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the
PHY Basic Control Register (PHY_BASIC_CONTROL) is set.
Note 11:
The default value of this bit is a 0 if in 100BASE-FX mode, otherwise the default value of this bit is deter-
mined by the Energy Efficient Ethernet Enable Strap (EEE_enable_strap_1). Refer to Section 7.0, "Config-
uration Straps," on page 54 for more information.
1
EDPD Extend Crossover
When in Energy Detect Power-Down (EDPD) mode (Energy Detect Power-
Down (EDPWRDOWN) = 1), setting this bit to 1 extends the crossover time
by 2976 ms.
0 = Crossover time extension disabled
1 = Crossover time extension enabled (2976 ms)
R/W
NASR
Note 10
0b
0
Extend Manual 10/100 Auto-MDIX Crossover Time
When Auto-Negotiation is disabled, setting this bit extends the Auto-MDIX
crossover time by 32 sample times (32 * 62 ms = 1984 ms). This allows the
link to be established with a partner PHY that has Auto-Negotiation enabled.
When Auto-Negotiation is enabled, this bit has no affect.
It is recommended that this bit is set when disabling AN with Auto-MDIX
enabled.
R/W
NASR
Note 10
1b
Bits
Description
Type
Default



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