LAN9250 datasheet(220/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 220

 2015 Microchip Technology Inc.

the MII Management Data (MDIO) signal and the MII Management Clock (MDC) signal. These signals allow access to

all PHY registers. Refer to Section 12.2.18, "PHY Registers," on page 230 for a list of all supported registers and register

descriptions. Non-supported registers will be read as FFFFh.

12.2.9

PHY INTERRUPTS

The PHY contains the ability to generate various interrupt events. Reading the PHY Interrupt Source Flags Register

(PHY_INTERRUPT_SOURCE) shows the source of the interrupt. The PHY Interrupt Mask Register (PHY_INTER-

RUPT_MASK) enables or disables each PHY interrupt.

The PHY Management Control block aggregates the enabled interrupts status into an internal signal which is sent to

the System Interrupt Controller and is reflected via the PHY Interrupt Event (PHY_INT) bit of the Interrupt Status Reg-

ister (INT_STS). For more information on the device interrupts, refer to Section 8.0, "System Interrupts," on page 62.

The PHY interrupt system provides two modes, a Primary interrupt mode and an Alternative interrupt mode. Both modes

will assert the internal interrupt signal sent to the System Interrupt Controller when the corresponding mask bit is set.

These modes differ only in how they de-assert the internal interrupt signal. These modes are detailed in the following

subsections.

12.2.9.1

Primary Interrupt Mode

The Primary interrupt mode is the default interrupt mode. The Primary interrupt mode is always selected after power-up

or hard reset. In this mode, to enable an interrupt, set the corresponding mask bit in the PHY Interrupt Mask Register

(PHY_INTERRUPT_MASK) (see Table 12-2). When the event to assert an interrupt is true, the internal interrupt signal

will be asserted. When the corresponding event to de-assert the interrupt is true, the internal interrupt signal will be de-

asserted.

Note:

The Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The Alternative

interrupt mode requires setup after a power-up or hard reset.

TABLE 12-2:

INTERRUPT MANAGEMENT TABLE

Mask

Interrupt Source Flag

Interrupt Source

Event to Assert

interrupt

Event to

De-assert interrupt

30.9

29.9

Link Up

LINKSTAT

See Note 1

Link Status

Rising LINK-

STAT

Falling LINKSAT or

Reading register 29

30.7

29.7

ENERGYON

17.1

ENERGYON

Rising 17.1

(Note 3)

Falling 17.1 or

Reading register 29

30.6

29.6

Auto-Negotia-

tion complete

1.5

Auto-Negoti-

ate Com-

plete

Rising 1.5

Falling 1.5 or

Reading register 29

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