LAN9250 datasheet(210/421 Pages) MICROCHIP

210 / 421 page

LAN9250

DS00001913A-page 210

 2015 Microchip Technology Inc.

12.0

ETHERNET PHY

12.1

Functional Overview

The device contains a PHY which connects to the Host MAC.

The PHY complies with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be configured for full/half

duplex 100 Mbps (100BASE-TX / 100BASE-FX) or 10 Mbps (10BASE-T) Ethernet operation. All PHY registers follow

the IEEE 802.3 (clause 22.2.4) specified MII management register set and are fully configurable.

12.1.1

PHY ADDRESSING

The default address for the PHY is fixed to 1.

In addition, the address for the PHY can be changed via the PHY Address (PHYADD) field in the PHY Special Modes

12.2

PHY

The device integrates two IEEE 802.3 PHY functions. The PHY can be configured for either 100 Mbps copper

(100BASE-TX), 100 Mbps fiber (100BASE-FX) or 10 Mbps copper (10BASE-T) Ethernet operation and includes Auto-

Negotiation and HP Auto-MDIX.

12.2.1

FUNCTIONAL DESCRIPTION

Functionally, the PHY can be divided into the following sections:

• 100BASE-TX Transmit and 100BASE-TX Receive

• 10BASE-T Transmit and 10BASE-T Receive

• Auto-Negotiation

• HP Auto-MDIX

• PHY Management Control and PHY Interrupts

• PHY Power-Down Modes and Energy Efficient Ethernet

• Resets

• Link Integrity Test

• Cable Diagnostics

• Loopback Operation

• 100BASE-FX Far End Fault Indication

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