ML7396AB datasheet(116/140 Pages) LAPIS

116 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

116/140

●Error process

●CRC Error

Case 1: CRC error occurs due to bit error

If CRC error occurs due to bit error, no need to read out Rx data from FIFO. By issuing PHY reset by [RST_SET:B0 0x01]

For details of FIFO clear, please refer to “FIFO clear” in “Flow Charts”.

Case 2: Out-of-sync detection after SFD detection (During Length, Data, CRC field receiving)

If out-of-syn is detected after SFD detection, CRC error interrupt (INT[20]/[21] group3) will be notified. However RX

completion interrput (INT[18]/[19] group3) will not be generated. If this case occurs, read Rx data that amount is specified

Length field from FIFO and then clearing CRC error interrpt.

START

RX_ON issue

[RF_STATUS:B0 0x6C]

RX completion (INT[18]/[19])?

[INT_SOURCE_GRP3:B0 0x26]

Yes

CRC error notification

([INT[20]/[21]]

[INT_SOURCE_GRP2:B0 0x25]

CRC error notification

([INT[20]/[21]]

[INT_SOURCE_GRP2:B0 0x25]

Read RX data from FIFO

[RD_RX_FIFO:B0 0x7F]

Read all Rx data?

PHY reset issue

[RST_SET:B0 0x01]

Clear INT[20] or [21]

[INT_SOURCE_GRP3:B0 0x26]

Yes

Clear INT[20]/[21]

[INT_SOURCE_GRP3:B0 0x26]

From RX flowchart

Yes

Note:

Be sure to clear the correct FIFO bank.

When issuing PHY reset, both FIFOs

are cleard.

Next packet RX?

TRX_OFF issue

[RF_STATUS:B0 0x6C]

END

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