ML7396AB datasheet(20/140 Pages) LAPIS

20 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

20/140

BANK0

Bit

Address

Symbol

(# test register)

Description

0x00

BANK_SEL

0x01

RST_SET

Software reset setting

0x02

CLK_SET

Clock configuration

0x03

CLKOUT

CLKOUT frequency setting

0x04

RATE_SET1

Data rate conversion setting 1

0x05

RATE_SET2

Data rate conversion setting 2

0x06-0x07

Reserved

0x08

#ADC_CLK_SET

RSSI ADC clock frequency setting

0x09-0x0a

Reserved

0x0b

#OSC_ADJ

Load capacitor adjustment for oscillation circuit

0x0c

#RF_TEST_MODE

TX test pattern setting

0x0d-0x0e

Reserved

0x0f

# PHY_STATE

PHY status indication

0x10

#FIFO_BANK

FIFO bank indication

0x11

#PLL_LOCK_DETECT

PLL lock detection configuration

0x12

CCA_IGNORE_LEVEL

ED threshold level setting for excluding CCA judgement

0x13

CCA_LEVEL

CCA threshold level setting

0x14

CCA_ABORT

Timing setting for forced termincation of CCA operation

0x15

CCA_CNTRL

CCA control setting and result indication

0x16

ED_RSLT

ED (Energy Detection) value indication

0x17

IDLE_WAIT_L

IDLE detection period setting during CCA (low 8bits)

0x18

IDLE_WAIT_H

IDLE detection period setting during CCA (high 2bits)

0x19

CCA_PROG_L

IDLE judgement elapsed time indication during CCA (low byte)

0x1a

CCA_PROG_H

IDLE judgement elapsed time indication during CCA (high 2bits)

0x1b

ED_CNTRL

ED detection control setting

0x1c

GAIN_MtoL

Threshold level setting for switching middle gain to low gain

0x1d

GAIN_LtoM

Threshold level setting for switching low gain to middle gain

0x1e

GAIN_HtoM

Gain update setting and threshold level setting for switching high gain to middle gain

0x1f

GAIN_MtoH

Threshold level setting for switching middle gain to high gain

0x20

RSSI_ADJ_M

RSSI offset value setting during middle gain operation

0x21

RSSI_ADJ_L

RSSI offset value setting during low gain operation

0x22

RSSI_STABLE_TIME

Time parameter for RSSI value become stable after gain switch

0x23

RSSI_VAL_ADJ

RSSI scale factor setting for ED value conversion.

0x24

INT_SOURCE_GRP1

FIFO clear setting and interrupt status for INT00 to INT05

0x25

INT_SOURCE_GRP2

Interrupt status for INT08 to INT15

0x26

INT_SOURCE_GRP3

Interrupt status for INT16 to INT23

0x27

INT_SOURCE_GRP4

Interrupt status for INT24 and INT25

0x28

PD_DATA_REQ

Data transmission request status indication

0x29

PD_DATA_IND

Data reception status indication

0x2a

INT_EN_GRP1

Interrupt mask for INT00 to INT05

0x2b

INT_EN_GRP2

Interrupt mask for INT08 to INT15

0x2c

INT_EN_GRP3

Interrupt mask for INT16 to INT23

0x2d

INT_EN_GRP4

Interrupt mask for INT24 and INT25

0x2e

CH_EN_L

RF channel enable setting for low 8ch

0x2f

CH_EN_H

RF channel enable setting for high 8ch

0x30

IF_FREQ_AFC_H

IF frequency setting during AFC operation (high byte)

0x31

IF_FREQ_AFC_L

IF frequency setting during AFC operation (low byte)

0x32

BPF_AFC_ADJ_H

Bandpass filter capacitance adjustment during AFC operation (high 2bits)

0x33

BPF_AFC_ADJ_L

Bandpass filter capacitance adjustment during AFC operation (low byte)

0x34

AFC_CNTRL

AFC control setting

0x35

TX_ALARM_LH

TX FIFO full level setting

0x36

TX_ALARM_HL

TX FIFO empty level setting

0x37

RX_ALARM_LH

RX FIFO full level setting

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