ML7396AB datasheet(48/140 Pages) LAPIS

48 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

48/140

The follwing is timing chart for IDLE detection.

[Upon BUSY detection, continue CCA and IDLE detection case]

[Conditions]

ADC_CK_SET ([ADC_CLK_SET:B0 0x08(4)])=0b1 (2MHz)

ED_AVG[2:0] ([ED_CNTRL:B0 0x1B(2-0)])=0b011 (ED value 8 times average)

IDLE_WAIT[9:0] ([IDLE_WAIT_L/H:B0 0x17/0x18(1-0)])=0b00_0000_0000 (IDLE detection 0μs)

After IDLE detection, CCA will be completed,

then CCA_EN, CCA_IDLE_EN are reset to

0b0 automatically..

CCA_EN/CCA_IDLE_EN

[Note]

1. After issuing CCA command, transit into no-input state, and exit this state after filter stbilization.

2. When the iput level chnge from no-input to -80dBm, it takes around 32 μs for indicating -80dBm ED value.

(21-28)

(22-29)

ED value average period

0b10 (CCA on-going)

ED0

ED7

ED8

ED28

[CCA_CTRL: B0 0x15(4-3)]

AD conversion

(16μs)

Filter stabilization

16 to 32 μs

IDLE detection period

0b00 (IDLE)

INVALID

ED value

ED27

ED29

●●●

(internal signal)

averaging

ED_Value[7:0]

CCA execution period (Min.128μs+IDLE detection period)

(20-27)

●●●

[ED_RSLT: B0 0x16]

(0-7)

(1-8)

<CCA_TH_LV

> CCA_TH_LV

B0 0x13

CCA_RSLT[1:0]

[CCA_CNTRL: B0 0x15(1-0)]

0b01 (BUSY)

If BUSY, Interrupt not generated

CCA_DONE

[CCA_CNTRL: B0 0x15(2)]

IDLE_WAIT[9:0]

should be set, for

IDLE detection for

longer period.

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