ML7396AB datasheet(7/140 Pages) LAPIS

7 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

7/140

PIN DEFINITION(continued)

●Miscellaneous pins

Pin name

Reset

state

I/O

Active

Level

Detail function

RESETN

Hardware reset

L: Hardware reset enable

H: normal operation

XIN

Ios

P or N

36MHz crystal pin1

*Fixed to GND in case of using external

clock

XOUT

Oos

P or N

36MHzcristal pin2

*Fixed to GND in case of using external

clock

TCXO

External clock (TCXO) input pin.

*Fixed to GND in case of using crystal

oscillator

ANT_SW

O/L

H or L or

Diversity control signal

TRX_SW

O/L

H or L or

TX-RX switch signal

TEST

Test mode input

Fixed to “L” for normal use

DMON*1

Digital monitor pin

Primary function: Clock output (6MHz)

Secondary function: PLL_LD output

Third function: FIFO trigger output

DCNT

O/L

H or L or

External TX PA control signal

31,35

N.C.

Non connection

[Description]

*1 Function of DMON pin can be selected by following condition. Clock output as a default.

If clock output is not used, please select another function. Please refer to each register description for more details.

Primary function will have higher priority when multiple function are configured simultaneously.

Configuration of DMON output

Function Name

Configuration register name

Address

Bit position (bit symbol)

CLK output

CLK_SET

B0 0x02

bit4 (CLKOUT_EN)

PLL_LD output

PLL_MON/DIO_SEL

B0 0x69

bit4 (PLL_LD)

FIFO trigger output

CRC_AREA/FIFO_TRG

B0 0x77

bit0 (FIFO_TRG_EN)

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