MT9072AB datasheet(194/275 Pages) ZARLINK

194 / 275 page

MT9072

Data Sheet

194

Zarlink Semiconductor Inc.

Bit Name

Functional Description

not used.

SLOL Loss of Sync Counter Overflow Latch. When the Loss of Sync Counter (SLC15-0 register

address Y16) overflows (3FF to 00), this status bit is latched to one. This bit is cleared when either

this register, or the interrupt status register (register address Y35) is read.

FEOL Frame Alignment Signal (FAS) Error Counter Overflow Latch. When the FAS Error Counter

(FEC7-0 register address Y1A lower byte) overflows (FF to 00), this status bit is latched to one.

This bit is cleared when either this register, or the interrupt status register (register address Y35) is

read.

FEIL

Frame Alignment Signal (FAS) Error Counter Indication Latch. When the FAS Error Counter

(FEC7-0 register address Y1A lower byte) is incremented by one, this status bit is latched to one.

This bit is cleared when either this register or the interrupt status register (register address Y35) is

read.

BEOL Frame Alignment Signal (FAS) Bit Error Counter Overflow Latch. When the FAS Bit Error

Counter (BEC7-0 register address Y1A upper byte) overflows (FF to 00), this status bit is latched to

one. This bit is cleared when either this register, or the interrupt status register (register address

Y35) is read.

BEIL

Frame Alignment Signal (FAS) Bit Error Counter Indication Latch. When the FAS Bit Error

Counter (BEC7-0 register address Y1A upper byte) is incremented by one, this status bit is latched

to one. This bit is cleared when either this register, or the interrupt status register (register address

Y35) is read.

9CEOL CRC-4 Error Counter Overflow Latch. When the CRC-4 Error Counter (CEC15-0 register

address Y19) overflows (3FF to 000), this status bit is latched to one. This bit is cleared when either

this register, or the interrupt status register (register address Y35) is read.

8CEIL

CRC-4 Error Counter Indication Latch. When the CRC-4 Error Counter (CEC15-0 register

address Y19) is incremented by one, this status bit is latched to one. This bit is cleared when either

this register, or the interrupt status register (register address Y35) is read.

7VEOL Bipolar Violation (BPV) Error Counter Overflow Latch. When the BPV Error Counter (VEC15-0

when either this register, or the interrupt status register (register address Y35) is read.

VEIL

Bipolar Violation (BPV) Error Counter Indication Latch. When the BPV Error Counter (VEC15-0

when either this register, or the interrupt status register (register address Y35) is read.

5EEOL E-Bit Error Counter Overflow Latch. When the E-Bit Error Counter (EEC15-0 register address

Y17) overflows (3FF to 000), this status bit is latched to one. This bit is cleared when either this

EEIL

E-Bit Error Counter Indication Latch. When the E-Bit Error Counter (EEC15-0 register address

Y17) is incremented by one, this status bit is latched to one. This bit is cleared when either this

3PCOL PRBS CRC-4 Counter Overflow Latch. When the PRBS CRC-4 Counter (PCC7-0 register

address Y15 lower byte) overflows (FF to 00), this status bit is latched to one. This bit is cleared

when either this register, or the interrupt status register (register address Y35) is read.

not used.

Table 170 - Counter Indication and Counter Overflow Latched Status Register (Address Y25) (E1)

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