MT9072AB datasheet(191/275 Pages) ZARLINK

191 / 275 page

MT9072

Data Sheet

191

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

6IDC

Idle Channel State. Is set to a 1 when an idle Channel state (15 or more ones) has been

detected at the receiver. This is an asynchronous event. On power reset, this may be 1 if

the clock (RXC) was not operating. Status becomes valid after the first 15 bits or the first

zero is received.

5-4

RQ9-8

RQ9-8 Byte Status bits from RX FIFO. These bits determine the status of the byte to be

read from RX FIFO as follows:

00 Packet Byte

01 First Byte

10 Last byte of good packet

11 Last byte of bad packet

3-2

TXSTAT1-0 Transmit FIFO Status:

00 Transmit FIFO is full.

01 The number of bytes in the transmit FIFO has reached or exceeded 16 bytes

10 Transmit FIFO is empty

11 The number of bytes in the TX FIFO is less than the 16 byte threshold.

1-0

RXSTAT1-0 Receive FIFO Status:

00 Receive FIFO is full.

01 The number of bytes in the Receive FIFO has reached or exceeded 16 bytes

10 Receive FIFO is empty

11 The number of bytes in the Receive FIFO is less than the 16 byte threshold.

Table 165 - HDLC Status Register(Y1D) (E1)

Bit

Name

Functional Description

15-0

RCRC15-0 Received CRC. The CRC received from the transmitter. The LSB of the FCS sequence is

MSB in this register. This register is updated at the end of each received packet and

therefore should be read when end of packet is detected.

Table 166 - HDLC Receive CRC(Y1E) (E1)

Bit

Name

Functional Description

7 - 0

RXFIFO7-0 Receive FIFO.This is the received data byte read from the RX FIFO. The status bits of

this byte can be read from the status register. The FIFO status is not changed

immediately when a write or read occurs. It is updated after the data has settled and the

transfer to the last available position has finished.

Table 167 - HDLC Receive FIFO(Y1F) (E1)

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