MT9072AB datasheet(35/275 Pages) ZARLINK

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MT9072

Data Sheet

Zarlink Semiconductor Inc.

163-178

A13,A14,

A15,A16,

B12,A12,

C12,D12,

A11,B11,

C11,D11,

C10,D10,

B10,A10

D0-D15

I/O Data 0 to 15. These 16 signals form the bidirectional data bus for the

non-multiplexed parallel processor interface. D15 is the most

significant bit.

181-192

B9,A9,C9,

D9,B8,C8,

A8,D8,D7,

B7,C7,A7

A0-A11

Address 0 to 11. These 12 signals form the input address bus for the

non-multiplexed parallel processor interface. Bits A10 and A8

determine which of the eight framers is selected for read and write

operations, bit A11 being high and A8 to A10 being low selects all

eight framers for write operations. A11 and A8 being both high and A9

being low selects global control registers. A11 is the most significant

bit.

193

Chip Select. A zero enables the read and write functions of the

MT9072 parallel processor interface; all bidirectional data bus lines

(D0-D15) will operate normally. A one disables the read and write

functions of the parallel processor interface; all bidirectional data

bus lines (D0-D15) will be in a high impedance state.

194

Data Strobe. Data Strobe for Motorola mode (I/M=0). The MT9072

reads data from the address bus (A0-A11) on the falling edge of DS;

writes data to the bidirectional data bus (D0-D15) on the falling edge

of DS (processor read); reads data from the bidirectional data bus

(D0-D15) on the falling edge of DS (processor write). DS may be

connected to CS.

(RD)I

Read. Read for Intel type mode (I/M=1). The MT9072 reads data

from the address bus (A0-A11) on the falling edge of RD; writes data

to the bidirectional data bus (D0-D15) on the falling edge of RD

(processor read).

195

R/W

Read/Write. Read and Write for Motorola mode (I/M=0). A zero sets

the MT9072 bidirectional data bus lines (D0-D15) as inputs for a

processor write. A one sets the MT9072 bidirectional data bus lines

(D0-D15) as outputs (processor read).

(WR)I

Write. Write for Intel type mode (I/M=1).

The MT9072 reads data

from the address bus (A0-A11) on the falling edge of WR; reads data

from the bidirectional data bus (D0-D15) on the rising edge of WR

(processor write).

196

IRQ

OH Interrupt Request. When zero, one or more of the eight framers in the

MT9072 has generated an interrupt request. When one, the MT9072

has not generated an interrupt request. IRQ is an open drain output

that should be connected to VDD through a pull-up resistor. CS can be

either high or low for this output pin to function.

Pin Description (continued)

Pin #

Name

Type

Description (see Notes 1 to 7)

LQFP

LBGA

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