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MT9072AB bảng dữ liệu(PDF) 82 Page - Zarlink Semiconductor Inc |
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MT9072AB bảng dữ liệu(HTML) 82 Page - Zarlink Semiconductor Inc |
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82 / 275 page ![]() MT9072 Data Sheet 82 Zarlink Semiconductor Inc. 10.1.7 Multiframe Boundary (RxMF, TxMF Pins) Dedicated multiframe boundary pins are included which provide the user the option of setting the multiframe boundaries and identifying the multiframe boundaries with an external device. Refer to the RxMF and TxMF pin descriptions for more details. 11.0 ST-BUS Analyzer The ST-BUS Analyzer is a powerful system diagnostic and debugging tool. The ST-BUS Analyzer allows for the capture of any ST-BUS data stream or channel to a 32 byte memory. The ST-BUS Analyzer can capture a single frame of data or 32 samples of a specified channel from DSTi, DSTo, CSTi or CSTo from any one of the 8 framers. The analysis can be performed continuously or on a single shot basis where 32 bytes are captured and then the analysis is suspended. An optional interrupt can be generated when a single shot analysis is complete. The operation of the ST-BUS analyzer is controlled by Global Control Register 1 (901). 12.0 Loopbacks 12.1 T1 Loopbacks In order to meet PRI Layer 1 requirements and to assist in circuit fault sectionalization, the MT9072 has 7 loopback functions. The control bits for digital, remote, ST-BUS and payload loopbacks are located at address Y05. The remote and local timeslot loopbacks are controlled through control bits of the Timeslot Control register located at addresses Y90-YA7. a) Digital loopback (DG Loop) - DSTi to DSTo at the PCM24 side. Bit DLBK = 0 normal; DLBK = 1 activate. b) Payload loopback (PL Loop) - Payload loopback (DSTo to DSTi). Bit PLBK = 0 normal; PLBK = 1 activate. The payload loopback is effectively a physical connection of DSTo to DSTi within the framer. Note: Set RxDO (YF1 bit 9 to 1) to obtain correct data at the Tx. c) Local and Remote Timeslot Loopback. Remote timeslot loopback control bit RTSL = 0 normal; RTSL = 1 activate (Register Y90-YA7) will loop around transmit ST-BUS timeslots to the DSTo stream. Local timeslot loopback bits LTSL = 0 normal; LTSL = 1 activate(Register Y90-YA7), will loop around receive PCM24 timeslots towards the remote PCM24 end. MT9072 Tx DSTi DSTo System PCM24 MT9072 Tx DSTi DSTo System PCM24 Rx |
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