MT9072AB datasheet(190/275 Pages) ZARLINK

190 / 275 page

MT9072

Data Sheet

190

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

BEC7

BEC6

BEC5

BEC4

BEC3

BEC2

BEC1

BEC0

Frame Alignment Signal (FAS) Bit Error Counter. These bits make up a counter which is

incremented for each individual error in the received PCM30 link basic frame alignment signal

(FAS) pattern (x0011011 in timeslot 0 of alternate frames). This counter is cleared with an

overflow, a RESET (RESET pin or RST bit), or it may be set by writing the desired value to it.

BEC0 is the least significant bit (LSB). The lower byte and upper byte of register cannot be written

to independently.

FEC7

FEC6

FEC5

FEC4

FEC3

FEC2

FEC1

FEC0

Frame Alignment Signal (FAS) Error Counter. These bits make up a counter which is

incremented for each combined (one or more) error in the received PCM30 link basic frame

alignment signal (FAS) pattern (x0011011 in timeslot 0 of alternate frames). This counter is

cleared with an overflow, a RESET (RESET pin or RST bit), or it may be set by writing the desired

value to it. FEC0 is the least significant bit (LSB). The lower byte and upper byte of register

cannot be written to independently.

Table 163 - Frame Alignment Signal (FAS) Bit Error Counter & FAS Error Counter (R/W Address Y1A)

(E1)

Bit

Name

Functional Description

15-12

####

not used.

RXclk

This bit represents the receiver clock generated after the RXEN control bit, but before

zero deletion is considered.

TXclk

This bit represents the transmit clock generated after the TXEN control bit, but before

zero insertion is considered.

Vcrc

This is the CRC recognition status bit for the receiver. Data is clocked into the register and

then this bit is monitored to see if comparison was successful (bit will be high).

Vaddr

This is the address recognition status bit for the receiver. Data is clocked into the Address

Recognition Register and then this bit is monitored to see if comparison was successful

(bit will be high).

7 - 0

TBP7-0

Transmit Byte Counter Position. These 7 bits provide the position of the Transmit HDLC

Byte Counter register (YF6). The counter is decremented as a byte of data is sent through

the Transmit FIFO.

When this register reaches the count of one, the next write to the Tx FIFO will be tagged

as an end of packet byte. The counter decrements at the end of the write to the Tx FIFO.

If the Cycle bit of YF2 is set high, the counter will cycle through the programmed value

continuously.

Table 164 - Transmit Byte Counter Position and HDLC Test Status(Y1C) (E1)

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