MT9072AB datasheet(187/275 Pages) ZARLINK

187 / 275 page

MT9072

Data Sheet

187

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

15-12

#### not used.

Phase Indicator. These 12 bits are an indication of the delay through the receive slip buffer

and the imminence of a receive frame slip. The read address is this register’s value plus 16 bits

and is updated when the write address is zero. The slip buffer contains 512 bits on 64 channels

(0 thru 63). The accuracy of this indicator is approximately 1/16 of a bit.

PI11

PI10

PI9

PI8

PI7

PI6

PI5

PI4

PI3

PI2

PI1

PI0

This bit indicates a 1 frame (32 timeslot or 256 bit) phase offset.

This bit indicates a 16 timeslot (128 bit) phase offset.

This bit indicates a 4 timeslot (64 bit) phase offset.

This bit indicates a 3 timeslot (32 bit) phase offset.

This bit indicates a 2 timeslot (16 bit) phase offset.

This bit indicates a 1 timeslot (8 bit) phase offset.

This bit indicates a 4 bit phase offset.

This bit indicates a 2 bit phase offset.

This bit indicates a 1 bit phase offset.

This bit indicates a 1/2 bit phase offset.

This bit indicates a 1/4 bit phase offset.

This bit indicates a 1/8 bit phase offset.

Table 157 - Phase Indicator Status (R Address Y14) (E1)

Bit

Name

Functional Description

PEC7

PEC6

PEC5

PEC4

PEC3

PEC2

PEC1

PEC0

Pseudo Random Bit Sequence (PRBS) Error Counter. These bits make up a counter which is

incremented for each pseudo random bit sequence (PRBS) (215-1) error detected on any of the

DSTo receive channels connected (ADSEQ=0 register address Y01, RRSTn=1 register address

Y90 to YAF) to the PRBS error detector. This counter is cleared with an overflow, a RESET

(RESET pin or RST bit), or may be set by writing the desired value to it. PEC0 is the least

significant bit (LSB). The lower byte and upper byte of register cannot be written to

independently.

PCC7

PCC6

PCC5

PCC4

PCC3

PCC2

PCC1

PCC0

Pseudo Random Bit Sequence (PRBS) CRC-4 Counter. These bits make up a counter which

is incremented for each received CRC-4 multiframe. This counter is cleared with an overflow, a

RESET (RESET pin or RST bit), or may be set by writing the desired value to it. PCC0 is the

least significant bit (LSB). The lower byte and upper byte of register cannot be written to

independently.

Table 158 - PRBS Error Counter & PRBS CRC-4 Counter (R/W Address Y15) (E1)

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