MT9072AB datasheet(198/275 Pages) ZARLINK

198 / 275 page

MT9072

Data Sheet

198

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

CEL15

CEL14

CEL13

CEL12

CEL11

CEL10

CEL9

CEL8

CEL7

CEL6

CEL5

CEL4

CEL3

CEL2

CEL1

CEL0

CRC-4 Error Count Latch. These bits make up a latch which samples the current value

of the CRC-4 Error Counter (address Y19) on the rising edge of the internal one second

timer (ONESEC register address Y11). This latch is cleared with a RESET (RESET pin

or RST bit). CEL0 is the least significant bit (LSB).

Table 175 - CRC-4 Error Count Latch (R/W Address Y2A) (E1)

Bit

Name

Functional Description

BEL7

BEL6

BEL5

BEL4

BEL3

BEL2

BEL1

BEL0

Frame Alignment Signal (FAS) Bit Error Count Latch. These bits make up a latch which

samples the current value of the Frame Alignment Signal (FAS) Bit Error Counter (upper

byte of address Y1A) on the rising edge of the internal one second timer (ONESEC

the least significant bit (LSB).

FEL7

FEL6

FEL5

FEL4

FEL3

FEL2

FEL1

FEL0

Frame Alignment Signal (FAS) Error Count Latch. These bits make up a latch which

samples the current value of the Frame Alignment Signal (FAS) Error Counter (lower byte

of address Y1A) on the rising edge of the internal one second timer (ONESEC register

address Y11). This latch is cleared with a RESET (RESET pin or RST bit). FEL0 is the

least significant bit (LSB).

Table 176 - Frame Alignment Signal (FAS) Error Count Latch (R/W Address Y2B) (E1)

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