COM20022ITQFP datasheet(71/83 Pages) SMSC

71 / 83 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

SMSC COM20022I

Page 71

Rev. 08-18-03

DATASHEET

A0-A2

VALID DATA

VALID

D0-D15

nCS

t10

Note 2

DIR

nDS

t11

nIOCS16

VALID VALUE

t12

t13

t6**

Parameter

min

max

units

t10

t11

t12

t13

4TARB

CASE 2: BUSTMG pin = LOW

Address Setup to nDS Active

Address Hold from nDS Inactive

nCS Setup to nDS Active

nCS Hold from nDS Inactive

DIR Setup to nDS Active

Cycle Time (nDS

to Next

)**

DIR Hold from nDS Inactive

Valid Data Setup to nDS High

Data Hold from nDS High

nDS Low Width

nDS High Width

nIOCS16 Output Delay from nCS Low

nIOCS16 Hold Delay from nCS High

0*****

40****

The Microcontroller typically accesses the COM20022 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20022 cycles.

Note 1:

**Note 2: Any cycle occurring after a write to the Address Pointer Low Register

requires a minimum of 4TARB from the trailing edge of nDS to the leading edge

of the next nDS.

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

**** t12 is measured from the latest active (valid) timing among nCS, A0-A2.

t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.

*****

Write cycle for Address Pointer Low Register occurring after an access to

Data Register requires a minimum of 5TARB from the trailing edge of nDS to

the leading edge of the next nDS.

Note 2 is applied to an access to Data Register by DMA transfer.

Figure 8.12 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle

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