COM20022ITQFP datasheet(31/83 Pages) SMSC

31 / 83 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

SMSC COM20022I

Page 31

Rev. 08-18-03

DATASHEET

Chapter 6 Functional Description

6.1

Microsequencer

The COM20022I contains an internal microsequencer which performs all of the control operations

necessary to carry out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program

counter, two instruction registers, an instruction decoder, a no-op generator, jump logic, and

reconfiguration logic.

The COM20022I derives a 20 MHz and a 10 MHz clock from the output clock of the Clock Multiplier.

These clocks provide the rate at which the instructions are executed within the COM20022I. The 20 MHz

clock is the rate at which the program counter operates, while the 10 MHz clock is the rate at which the

instructions are executed. The microprogram is stored in the ROM and the instructions are fetched and

then placed into the instruction registers. One register holds the opcode, while the other holds the

immediate data. Once the instruction is fetched, it is decoded by the internal instruction decoder, at which

point the COM20022I proceeds to execute the instruction. When a no-op instruction is encountered, the

microsequencer enters a timed loop and the program counter is temporarily stopped until the loop is

complete. When a jump instruction is encountered, the program counter is loaded with the jump address

from the ROM.

The COM20022I contains an internal reconfiguration timer which interrupts the

microsequencer if it has timed out. At this point the program counter is cleared and the MYRECON bit of

the Diagnostic Status Register is set.

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