CP3SP33SMSSLASHNOPB datasheet(345/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

33.2.8 Counter Register x Module n (COUNTx_n)

The COUNTx_n registers are 16-bit, read/write registers. There are four registers in each module, called

COUNT1_n through COUNT4_n, one for each of the four timer subsystems. Software may read the

registers at any time. Reading the register will return the current value of the counter. The register may

only be written if the counter is stopped (i.e., if both TxRUN bits associated with a timer sub- system are

clear). The registers are cleared at reset.

CNTx

33.2.9 Period/Capture Register x Module n (PERCAPx_n)

The PERCAPx_n registers are 16-bit, read/write registers. There are four registers called PERCAP1_n

through PERCAP4_n, one for each timer subsystem. The registers hold the period compare value in PWM

mode of the counter value at the time the last associated capture event occurred. In PWM mode the

will not take effect until counter value matches the previous period compare value or until the counter is

stopped. Reading may take place at any time and will return the most recent value which was written. The

PERCAPx_n registers are cleared at reset.

PCAPx

33.2.10 Duty Cycle/Capture Register x Module n (DTYCAPx_n)

The DTYCAPx_n registers are 16-bit, read/write registers. There are four registers called DTYCAP1_n

through DTYCAP4_n, one for each timer subsystem. The registers hold the period compare value in PWM

mode or the counter value at the time the last associated capture event occurred. In PWM mode, the

write will not take effect until the counter value matches the previous period compare value or until the

counter is stopped. The update takes effect on period boundaries only. Reading may take place at any

time and will return the most recent value which was written. The DTYCAPx_n registers are cleared at

reset.

DCAPx

34 Register Map

Table 34-1 is a detailed memory map showing the specific memory address of the memory, I/O ports, and

registers. The table shows the starting address, the size, and a brief description of each memory block

and register. For detailed information on using these memory locations, see the applicable sections in the

data sheet.

All addresses not listed in the table are reserved and must not be read or written. An attempt to access an

unlisted address will have unpredictable results.

Each byte-wide register occupies a single address and can be accessed only in a byte-wide transaction.

Each wordwide register occupies two consecutive memory addresses and can be accessed only in a

word-wide transaction. Both the byte-wide and word-wide registers reside at word boundaries (even

addresses). Therefore, each byte-wide register uses only the lowest eight bits of the internal data bus.

Most device registers are read/write registers. However, some registers are read-only or write-only, as

indicated in the table. An attempt to read a write-only register or to write a read-only register will have

unpredictable results.

345

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