CP3SP33SMSSLASHNOPB datasheet(342/407 Pages) TI1

342 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

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0 – Timer stopped.

1 – Timer running.

TMODx The Timer System Operating Mode field enables or disables the Timer Subsystem and defines

its operating mode.

00 Low-Power Mode. All clocks to the counter subsystem are stopped. The counter is

– stopped regardless of the value of the TxRUN bits. Read operations to the Timer

Subsystem will return the last value; software must not perform any write operations to the

Timer Subsystem while it is disabled since those will be ignored.

01 Dual 8-bit PWM mode. Each 8-bit counter may individually be started or stopped via its

– associated TxRUN bit. The TIOn_y pins will function as PWM outputs.

10 16-bit PWM mode. The two 8-bit counters are concatenated to form a single 16-bit

– counter. The counter may be started or stopped with the lower of the two TxRUN bits, i.e,.

T1RUN, T3RUN, T5RUN, and T7RUN. The TIOn_y pins will function as PWM outputs.

11 Capture Mode. Both 8-bit counters are concatenated and operate as a single 16-bit

– counter. The counter may be started or stopped with the lower of the two TxRUN bits, i.e.,

T1RUN, T3RUN, T5RUN, and T7RUN. The TIOn_y pins will function as capture inputs.

33.2.2 I/O Control Register 1 Module n (IO1CTL_n)

The IO1CTL_n registers are 16-bit, read/write registers. The registers control the I/O pins TIOn_1 through

TIOn_4 depending on the selected mode of operation. The registers are clear after reset.

P4POL

C4EDG

P3POL

C3EDG

P2POL

C2EDG

P1POL

C2EDG

CxEDG The Capture Edge Control field specifies the polarity of a capture event and the reset of the

counter. The value of this three bit field has no effect while operating in PWM mode.

CxEDG

CAPTURE

COUNTER RESET

000

Rising edge

001

Falling edge

010

Rising edge

Yes

011

Falling edge

Yes

100

Both edges

101

Both edges

Rising edge

110

Both edges

Falling edge

111

Both edges

PxPOL

The PWM Polarity bit selects the output polarity. While operating in PWM mode the bit specifies

the polarity of the corresponding PWM output (TIOn_y). Once a counter is stopped, the output

will assume the value of PxPOL, i.e., its initial value. The PxPOL bit has no effect while

operating in capture mode.

0 – The PWM output goes high at the 00h to 01h transition of the counter and will go low

once the counter value matches the duty cycle value.

1 – The PWM output goes low at the 00h to 01h transition of the counter and will go high

once the counter value matches the duty cycle value.

33.2.3 I/O Control Register 2 Module n (IO2CTL_n)

The IO2CTL_n registers are 16-bit, read/write registers. The registers control the I/O pins TIOn_5 through

TIOn_8 depending on the selected mode of operation. The registers are cleared at reset.

342

Dual Versatile Timer Units (VTU)

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