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CS8900A bảng dữ liệu(PDF) 52 Page - Cirrus Logic |
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CS8900A bảng dữ liệu(HTML) 52 Page - Cirrus Logic |
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52 / 128 page ![]() 52 DS271PP3 CS8900A Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATA SHEET 4.4.5 Register 0: Interrupt Status Queue (ISQ, Read-only, Address: PacketPage base + 0120h) The Interrupt Status Queue Register is used in both Memory Mode and I/O Mode to provide the host with interrupt information. Whenever an event occurs that triggers an enabled interrupt, the CS8900A sets the appropriate bit(s) in one of five registers, maps the contents of that register to the ISQ register, and drives an IRQ pin high. Three of the registers mapped to ISQ are event registers: RxEvent (Register 4), TxEvent (Register 8), and BufEvent (Register C). The other two registers are counter-overflow reports: RxMISS (Register 10) and TxCOL (Register 12). In Mem- ory Mode, ISQ is located at PacketPage base + 120h. In I/O Mode, ISQ is located at I/O Base + 0008h. See Section 5.1 on page 79. RegNum The lower six bits describe which register (4, 8, C, 10 or 12) is contained in the ISQ. RegContent The upper ten bits contain the register data contents. Reset value is: 0000 0000 0000 0000 765 4321 0 RegContent RegNum F E DCBA 9 8 RegContent |
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