CS8900A datasheet(74/128 Pages) CIRRUS

74 / 128 page

DS271PP3

CS8900A

Crystal LAN™ ISA Ethernet Controller

CIRRUS LOGIC PRODUCT DATA SHEET

Failure to observe these three rules may cause data

corruption.

4.8.1 Transferring Odd-Byte-Aligned Data

Some applications gather transmit data from more

than one section of host memory. The boundary be-

tween the various memory locations may be either

even- or odd-byte aligned. When such a boundary

is odd-byte aligned, the host should transfer the last

byte of the first block to an even address, followed

by the first byte of the second block to the follow-

ing odd address. It can then resume word transfers.

An example of this is shown in Figure 17.

4.8.2 Random Access to CS8900A Memory

The first 118 bytes of a receive frame held in the

CS8900A’s on-chip memory may be randomly ac-

cessed in Memory mode. After the first 118 bytes,

only sequential access of received data is allowed.

Either byte or word access is permitted, as long as

all word accesses are executed to even-byte bound-

aries.

4.9 Memory Mode Operation

To configure the CS8900A for Memory Mode, the

PacketPage memory must be mapped into a contig-

uous 4-kbyte block of host memory. The block

must start at an X000h boundary, with the Pack-

etPage base address mapped to X000h. When the

CS8900A comes out of reset, its default configura-

tion is I/O Mode. Once Memory Mode is selected,

all of the CS8900A’s registers can be accessed di-

rectly.

In Memory Mode, the CS8900A supports Standard

or Ready Bus cycles without introducing additional

wait states.

Memory moves can use MOVD (double-word

transfers) as long as the CS8900A’s memory base

address is on a double word boundary. Since 286

processors don’t support the MOVD instruction,

word and byte transfers must be used with a 286.

4.9.1 Accesses in Memory Mode

The CS8900A allows Read/Write access to the in-

ternal PacketPage memory, and Read access of the

optional Boot PROM. (See Section 3.7 on page 26

for a description of the optional Boot PROM.)

A memory access occurs when all of the following

are true:

•

The address on the ISA System Address bus

(SA0 - SA19) is within the Memory space

range of the CS8900A or Boot PROM.

•

The CHIPSEL input pin is low.

•

Either the MEMR pin or the MEMW pin is low.

4.9.2 Configuring the CS8900A for Memory

Mode

There are two different methods of configuring the

CS8900A for Memory Mode operation. One meth-

od allows the CS8900A's internal memory to be

mapped anywhere within the host system's 24-bit

Word Transfer

Byte Transfer

Word Transfer

Byte Transfer

Word Transfer

First Block of Data

Second Block of Data

Figure 17. Odd-Byte Aligned Data

Description Mnemonic Read/Write

Location:

PocketPage

base +

Receive

Status

RxStatus

Read-only

0400h-0401h

Receive

Length

RxLength

Read-only

0402h-0403h

Receive

Frame

RxFrame

Read-only starts at 0404h

Transmit

Frame

TxFrame

Write-only starts at 0A00h

Table 16. Receive/Transmit Memory Locations

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