CS8900A datasheet(99/128 Pages) CIRRUS

99 / 128 page

DS271PP3

CS8900A

Crystal LAN™ ISA Ethernet Controller

CIRRUS LOGIC PRODUCT DATA SHEET

5.7 Transmit Operation

5.7.1 Overview

Packet transmission occurs in two phases. In the

first phase, the host moves the Ethernet frame into

the CS8900A’s buffer memory. The first phase be-

gins with the host issuing a Transmit Command.

This informs the CS8900A that a frame is to be

transmitted and tells the chip when (i.e. after 5,

381, or 1021 bytes have been transferred or after

the full frame has been transferred to the CS8900A)

and how the frame should be sent (i.e. with or with-

out CRC, with or without pad bits, etc.). The host

follows the Transmit Command with the Transmit

Length, indicating how much buffer space is re-

quired. When buffer space is available, the host

writes the Ethernet frame into the CS8900A’s inter-

nal memory, using either Memory or I/O space.

In the second phase of transmission, the CS8900A

converts the frame into an Ethernet packet then

transmits it onto the network. The second phase be-

gins with the CS8900A transmitting the preamble

and Start-of-Frame delimiter as soon as the proper

number of bytes has been transferred into its trans-

mit buffer (5, 381, 1021 bytes or full frame, de-

pending on configuration). The preamble and Start-

of-Frame delimiter are followed by the data trans-

ferred into the on-chip buffer by the host (Destina-

tion Address, Source Address, Length field and

LLC data). If the frame is less than 64 bytes, in-

cluding CRC, the CS8900A adds pad bits if config-

ured to do so. Finally, the CS8900A appends the

proper 32-bit CRC value.

5.7.2 Transmit Configuration

After each reset, the CS8900A must be configured

for transmit operation. This can be done automati-

cally using an attached EEPROM, or by writing

configuration commands to the CS8900A’s internal

registers (see Section 3.4 on page 21). The items

that must be configured include which physical in-

terface to use and which transmit events cause in-

terrupts.

5.7.2.1 Configuring the Physical Interface

Configuring the physical interface consists of de-

termining which Ethernet interface should be ac-

tive (10BASE-T or AUI), and enabling the transmit

logic for serial transmission. Configuring the Phys-

ical Interface is accomplished via the LineCTL reg-

ister (Register 13) and is described in Table 30.

Note that the CS8900A transmits in 10BASE-T

mode when no link pulses are being received only

if bit DisableLT is set in register Test Control (Reg-

ister 19).

5.7.2.2 Selecting which Events Cause Interrupts

The TxCFG register (Register 7) and the BufCFG

transmit events will cause interrupts to the host pro-

cessor. Tables 31 and 32 describe the interrupt en-

able (iE) bits in these registers.

5.7.3 Changing the Configuration

When the host configures these registers it does not

need to change them for subsequent packet trans-

missions. If the host does choose to change the Tx-

CFG or BufCFG registers, it may do so at any time.

The effects of the change are noticed immediately.

That is, any changes in the Interrupt Enable (iE)

bits may affect the packet currently being transmit-

ted.

Bit

Bit Name

Operation

SerTxON

When set, transmission enabled.

AUIonly

When set, AUI selected (takes

precedence over AutoAUI/10BT).

When clear, 10BASE-T selected.

AutoAUI/10BT When set, automatic interface

selection enabled.

BMod

BackoffE

When set, the modified backoff

algorithm is used. When clear,

the standard backoff algorithm is

used.

D2-part

DefDis

When set, two-part deferral is

disabled.

Table 30. Physical Interface Configuration

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