CS8900A datasheet(59/128 Pages) CIRRUS

59 / 128 page

DS271PP3

CS8900A

Crystal LAN™ ISA Ethernet Controller

CIRRUS LOGIC PRODUCT DATA SHEET

4.4.12 Register B: Buffer Configuration

(BufCFG, Read/Write, Address: PacketPage base + 010Ah)

Each bit in BufCFG is an interrupt enable. When set, the interrupt described below is enabled. When clear, there is

no interrupt.

001011

These bits provide an internal address used by the CS8900A to identify this as the Buffer Con-

figuration Register.

SWint-X

When set, there is an interrupt requested by the host software. The CS8900A provides the in-

terrupt, and sets the SWint (Register C, BufEvent, Bit 6) bit. The CS8900A acts upon this com-

mand at once. SWint-X is an Act-Once bit. To generate another interrupt, rewrite a "1" to this bit.

RxDMAiE

When set, there is an interrupt when a frame has been received and DMA is complete. With

this interrupt, the RxDMAFrame bit (Register C, BufEvent, Bit 7) is set.

Rdy4TxiE

When set, there is an interrupt when the CS8900A is ready to accept a frame from the host for

transmission. (See Section 5.7 on page 99 for a description of the transmit bid process.)

TxUnderruniE

When set, there is an interrupt if the CS8900A runs out of data before it reaches the end of the

frame (called a transmit underrun). When this happens, event bit TXUnderrun (Register C,

BufEvent, Bit 9) is set and the CS8900A makes no further attempts to transmit that frame. If the

host still wants to transmit that particular frame, the host must go through the transmit request

process again.

RxMissiE

When set, there is an interrupt if one or more received frames is lost due to slow movement of

receive data out of the receive buffer (called a receive miss). When this happens, the RxMiss

bit (Register C, BufEvent, Bit A) is set.

Rx128iE

When set, there is an interrupt after the first 128 bytes of a frame have been received. This al-

lows a host processor to examine the Destination Address, Source Address, Length, Sequence

Number, and other information before the entire frame is received. This interrupt should not be

used with DMA. Thus, if either AutoRxDMA (Register 3, RxCFG, Bit A) or RxDMAonly (Register

3, RxCFG, Bit 9) is set, the Rx128iE bit must be clear.

TxColOvfiE

If set, there is an interrupt when the TxCOL counter increments from 1FFh to 200h. (The TxCOL

counter (Register 18) is incremented whenever the CS8900A sees that the RXD+/RXD- pins

(10BASE-T) or the CI+/CI- pins (AUI) go active while a packet is being transmitted.)

MissOvfloiE

If MissOvfloiE is set, there is an interrupt when the RxMISS counter increments from 1FFh to

200h. (A receive miss is said to have occurred if packets are lost due to slow movement of re-

ceive data out of the receive buffers. When this happens, the RxMiss bit (Register C, BufEvent,

Bit A) is set, and the RxMISS counter (Register 10) is incremented.)

RxDestiE

When set, there is an interrupt when a receive frame passes the Destination Address filter cri-

teria defined in the RxCTL register (Register 5). This bit provides an early indication of an in-

coming frame. It is earlier than Rx128 (Register C, BufEvent, Bit B). If RxDestiE is set, the

BufEvent could be RxDest or Rx128. After 128 bytes are received, the BufEvent changes from

RxDest to Rx128.

After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state after reset. If an

EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19.

Reset value is: 0000 0000 0000 1011

765

4321

RxDMAiE

SWint-X

001011

DCBA

RxDestiE

Miss OvfloiE

TxCol OvfloiE

Rx128iE

RxMissiE

TxUnder runtiE

Rdy4TxiE

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