CS8900A datasheet(39/128 Pages) CIRRUS

39 / 128 page

DS271PP3

CS8900A

Crystal LAN™ ISA Ethernet Controller

CIRRUS LOGIC PRODUCT DATA SHEET

4.0 PACKETPAGE ARCHITECTURE

4.1 PacketPage Overview

The CS8900A architecture is based on a unique,

highly-efficient method of accessing internal regis-

ters and buffer memory known as PacketPage.

PacketPage provides a unified way of controlling

the CS8900A in Memory or I/O space that mini-

mizes CPU overhead and simplifies software. It

provides a flexible set of performance features and

configuration options, allowing designers to devel-

op Ethernet circuits that meet their particular sys-

tem requirements.

4.1.1 Integrated Memory

Central to the CS8900A architecture is a 4-Kbyte

page of integrated RAM known as PacketPage

memory. PacketPage memory is used for tempo-

rary storage of transmit and receive frames, and for

internal registers. Access to this memory is done

directly,

through

Memory

space

operations

(Section 4.9 on page 74), or indirectly, through I/O

space operations (Section 4.10 on page 76). In

most cases, Memory Mode will provide the best

overall performance, because ISA Memory opera-

tions require fewer cycles than I/O operations. I/O

Mode is the CS8900A’s default configuration and

is used when memory space is not available or

when special operations are required (e.g. waking

the CS8900A from the Software Suspend State re-

quires the host to write to the CS8900A’s assigned

I/O space).

The user-accessible portion of PacketPage memory

is organized into the following six sections:

4.1.2 Bus Interface Registers

The Bus Interface registers are used to configure

the CS8900A’s ISA-bus interface and to map the

CS8900A into the host system’s I/O and Memory

space. Most of these registers are written only dur-

ing initialization, remaining unchanged while the

CS8900A is in normal operating mode. The excep-

tions to this are the DMA registers which are mod-

ified continually whenever the CS8900A is using

DMA. These registers are described in more detail

in Section 4.3 on page 42.

4.1.3 Status and Control Registers

The Status and Control registers are the primary

means of controlling and getting status of the

CS8900A. They are described in more detail in

Section 4.4 on page 47.

4.1.4 Initiate Transmit Registers

The TxCMD/TxLength registers are used to initiate

Ethernet frame transmission. These registers are

described in more detail in Section 4.5 on page 71.

(See Section 5.7 on page 99 for a description of

frame transmission.)

4.1.5 Address Filter Registers

The Filter registers store the Individual Address fil-

ter and Logical Address filter used by the Destina-

tion Address (DA) filter. These registers are

described in more detail in Section 4.6 on page 72.

For a description of the DA filter, see Section 5.3

on page 87.

4.1.6 Receive and Transmit Frame Locations

The Receive and Transmit Frame PacketPage loca-

tions are used to transfer Ethernet frames to and

from the host. The host simply writes to and reads

from these locations and internal buffer memory is

dynamically allocated between transmit and re-

ceive as needed. This provides more efficient use

of buffer memory and better overall network per-

formance. As a result of this dynamic allocation,

only one receive frame (starting at PacketPage base

+ 0400h) and one transmit frame (starting at Pack-

PacketPage

Address

Contents

0000h - 0045h

Bus Interface Registers

0100h - 013Fh

Status and Control Registers

0140h - 014Fh

Initiate Transmit Registers

0150h - 015Dh

Address Filter Registers

0400h

Receive Frame Location

0A00h

Transmit Frame Location

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