PI7C7300DNA datasheet(95/107 Pages) PERICOM

95 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 95 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

15.1

BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES

Initiator

Target

Response

Master on Primary

Target on Primary

PI7C7300D does not respond. It detects

this situation by decoding the address as

well as monitoring the P_DEVSEL# for

other fast and medium devices on the

Primary Port.

Master on Primary

Target on Secondary

PI7C7300D asserts P_DEVSEL#,

terminates the cycle normally if it is able

to be posted, otherwise return with a retry.

It then passes the cycle to the appropriate

port. When the cycle is complete on the

target port, it will wait for the initiator to

repeat the same cycle and end with normal

termination.

Master on Primary

Target not on Primary nor

Secondary Port

PI7C7300D does not respond and the

cycle will terminate as master abort.

Master on Secondary

Target on the same

Secondary Port

PI7C7300D does not respond.

Master on Secondary

Target on Primary or the

other Secondary Port

PI7C7300D asserts S1_DEVSEL# or

S2_DEVSEL#, terminates the cycle

normally if it is able to be posted,

otherwise returns with a retry. It then

passes the cycle to the appropriate port.

When cycle is complete on the target port,

it will wait for the initiator to repeat the

same cycle and end with normal

termination.

Master on Secondary

Target not on Primary nor

the other Secondary Port

PI7C7300D does not respond.

15.2

TRANSACTION ORDERING

To maintain data coherency and consistency, PI7C7300D complies with the ordering

rules put forth in the PCI Local Bus Specification, Rev 2.2. The following table

summarizes the ordering relationship of all the transactions through the bridge.

PMW - Posted write (either memory write or memory write & invalidate)

DRR - Delayed read request (all memory read, I/O read & configuration read)

DWR - Delayed write request (I/O write & configuration write, memory write to

certain location)

DRC - Delayed read completion (all memory read, I/O read & configuration read)

DWC - Delayed write completion (I/O write & configuration write, memory write

to ccertain location

Cycle type shown on each row is the subsequent cycle after the previous shown on the

column.

Can Row Pass Column?

PMW

Column 1

DRR

Column 2

DWR

Column 3

DRC

Column 4

DWC

Column 5

PMW (Row 1)

Yes

DRR (Row 2)

Yes

DWR (Row 3)

Yes

DRC (Row 4)

Yes

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