PI7C7300DNA datasheet(91/107 Pages) PERICOM

91 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 91 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

14.1.38

MASTER TIMEOUT COUNTER REGISTER – OFFSET 74h

Bit

Function

Type

Description

31:16

Master Timeout

R/W

Holds the maximum number of PCI clocks that PI7C7300D will wait

for initiator to retry the same cycle before reporting timeout. Master

timeout occurs after 2

10 PCI clocks.

Default is 400h.

14.1.39

RETRY COUNTER REGISTER – OFFSET 78h

Bit

Function

Type

Description

31:0

Retry Counter

R/W

Holds the maximum number of attempts that PI7C7300D will try

before reporting retry timeout. Retry count set at 2

24 PCI clocks.

Default is 0100 0000h.

14.1.40

SAMPLING TIMER REGISTER – OFFSET 7Ch

Bit

Function

Type

Description

31:0

Sampling Timer

R/W

Sets the duration (in PCI clocks) during which PI7C7300D will

record the number of successful transactions for performance

evaluation. The recording will start right after this register is

programmed and will be cleared after the timer expires. Maximum

period is 128 seconds at 33MHz.

Reset to 0.

14.1.41

SECONDARY SUCCESSFUL I/O READ COUNTER REGISTER –

OFFSET 80h

Bit

Function

Type

Description

31:0

Successful I/O

Read Counts on

S1 or S2

R/W

Stores the successful I/O read count on S1 or S2 and is updated when

the sampling timer is active.

Reset to 0

14.1.42

SECONDARY SUCCESSFUL I/O WRITE COUNTER REGISTER –

OFFSET 84h

Bit

Function

Type

Description

31:0

Successful I/O

Write Counts on

S1 or S2

R/W

Stores the successful I/O write count on S1 or S2 and is updated

when the sampling timer is active.

Reset to 0

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