PI7C7300DNA datasheet(45/107 Pages) PERICOM

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PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 45 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

5.2.2

ISA MODE

PI7C7300D supports ISA mode by providing an ISA enable bit in the bridge control

the I/O address range in order to support mapping of I/O space in the presence of an ISA

bus in the system. This bit only affects the response of PI7C7300D when the transaction

falls inside the address range defined by the I/O base and limit address registers, and only

when this address also falls inside the first 64KB of I/O space (address bits [31:16] are

0000h). When the ISA enable bit is set, PI7C7300D does not forward downstream any

I/O transactions addressing the top 768 bytes of each aligned 1KB block. Only those

transactions addressing the bottom 256 bytes of an aligned 1KB block inside the base

and limit I/O address range are forwarded downstream. Transactions above the 64KB I/O

address boundary are forwarded as defined by the address range defined by the I/O base

and limit registers.

Accordingly, if the ISA enable bit is set, PI7C7300D forwards upstream those I/O

transactions addressing the top 768 bytes of each aligned 1KB block within the first

64KB of I/O space. The master enable bit in the command configuration register must

also be set to enable upstream forwarding. All other I/O transactions initiated on the

secondary bus are forwarded upstream only if they fall outside the I/O address range.

When the ISA enable bit is set, devices downstream of PI7C7300D can have I/O space

mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or

anywhere in I/O space above the 64KB boundary.

5.3

MEMORY ADDRESS DECODING

PI7C7300D has three mechanisms for defining memory address ranges for forwarding of

memory transactions:

Memory-mapped I/O base and limit address registers

Prefetchable memory base and limit address registers

VGA mode

This section describes the first two mechanisms. Section 5.4.1 describes VGA mode. To

enable downstream forwarding of memory transactions, the memory enable bit must be

set in the command register in configuration space. To enable upstream forwarding of

memory transactions, the master-enable bit must be set in the command register. The

master-enable bit also allows upstream forwarding of I/O transactions if it is set.

CAUTION

If any configuration state affecting memory transaction forwarding is changed by a

configuration write operation on the primary bus at the same time that memory

transactions are ongoing on the secondary bus, response to the secondary bus memory

transactions is not predictable. Configure the memory-mapped I/O base and limit

address registers, prefetchable memory base and limit address registers, and VGA

mode bit before setting the memory enable and master enable bits, and change them

subsequently only when the primary and secondary PCI buses are idle.

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