PI7C7300DNA datasheet(82/107 Pages) PERICOM

82 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 82 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

14.1.19

PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h

Bit

Function

Type

Description

3:0

64-bit addressing

R/O

Indicates 64-bit addressing

0000: 32-bit addressing

0001: 64-bit addressing

Reset to 1

15:4

Prefetchable

Memory Base

Address [31:20]

R/W

Defines the bottom address of an address range for the bridge to

determine when to forward memory read and write transactions from

one interface to the other. The upper 12 bits correspond to address

bits [31:20] and are writable. The lower 20 bits are assumed to be 0.

14.1.20

PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h

Bit

Function

Type

Description

19:16

64-bit addressing

R/O

Indicates 64-bit addressing

0000: 32-bit addressing

0001: 64-bit addressing

Reset to 1

31:20

Prefetchable

Memory Base

Address [31:20]

R/W

Defines the top address of an address range for the bridge to

determine when to forward memory read and write transactions from

one interface to the other. The upper 12 bits correspond to address

bits [31:20] and are writable. The lower 20 bits are assumed to be

FFFFFh.

14.1.21

PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS

Bit

Function

Type

Description

31:0

Prefetchable

Memory Base

Address, Upper

32-bits [63:32]

R/W

Defines the upper 32-bits of a 64-bit bottom address of an address

range for the bridge to determine when to forward memory read and

write transactions from one interface to the other.

Reset to 0

14.1.22

PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS

Bit

Function

Type

Description

31:0

Prefetchable

Memory Limit

Address, Upper

32-bits [63:32]

R/W

Defines the upper 32-bits of a 64-bit top address of an address range

for the bridge to determine when to forward memory read and write

transactions from one interface to the other.

Reset to 0

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