UCC24636DBVT datasheet(12/35 Pages) TI1

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UCC24636

SLUSCG2A – MARCH 2016 – REVISED MARCH 2016

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Feature Description (continued)

The UCC24636 uses the VPC and VSC pins to sense the SR MOSFET VDS voltage and converter VOUT voltage

through resistor dividers. The information of VIN/NPS, tPRI, and VOUT can be obtained from the information on VPC

and VSC pins. The SR MOSFET turn on is determined when the SR MOSFET body diode starts conducting and

the VPC pin voltage falls to near zero; the SR MOSFET turn off is determined by the current emulator control

ramps.

The UCC24636 volt-sec control generates the internal VPC ramp and VSC ramp to emulate the transformer Volt-

Sec balancing as shown in Figure 13.

The secondary current discharge time, tSEC-DIS can be determined indirectly. The primary volt-sec ramp and

secondary volt-sec ramp both start when VPC rises above VVPC-EN and VVPC-TH. The charge currents for the VPC

and VSC ramps are determined by the voltage on the VPC and VSC pins respectively.

When VPC is higher than VVPC-EN and VVPC-TH for t > tVPC-BLK, the VPC pulse is qualified as a primary conduction

pulse and the SR can be enabled on the VPC falling edge. The VPC ramp continues to rise until the VPC falling

edge based on the real time voltage on the VPC pin and holds the peak for the cycle. The DRV output is turned

on during the VPC falling edge near zero volts, and DRV is turned off when the VSC rising ramp crosses the

VPC ramp held level.

Both VPC and VSC ramps are reset to zero on each VPC rising edge above the VVPC-EN and VVPC-TH thresholds.

To discriminate primary on-time pulses from DCM ringing, there are voltage and time criteria that must be

satisfied on the VPC pin to enable the DRV output. tVPC-BLK can be adjusted through the resistor on TBLK pin.

At the rising edge of VPC when the voltage exceeds VVPC-EN and VVPC-TH the blanking time tVPC-BLK is initiated. At

the end of tVPC-BLK, the VPC voltage is sampled during tVPC-SPL window, which is 100 ns nominal. Also at the end

of tVPC-BLK, the DRV output can be enabled.

The VPC voltage sampled during tVPC-SPL determines the VPC dynamic threshold VVPC-TH which is normally 85%

of the sampled VPC voltage. The dynamic threshold provides the ability to reject the DCM ringing and detect the

primary on-time. Noise immunity during the turn-on event of DRV at the falling edge of the VPC pin is enhanced

by a minimum DRV on time of tSRONMIN, which is 350 ns nominal.

During the falling edge of DRV, the tOFF timer is initiated which inhibits turn on of the SR until tOFF expires. This

eliminates false turn on of DRV if the DCM ringing is close to ground.

UCC24636DBVT bảng dữ liệu(PDF) 12 Page - Texas Instruments