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UCC24636DBVT bảng dữ liệu(PDF) 19 Page - Texas Instruments |
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UCC24636DBVT bảng dữ liệu(HTML) 19 Page - Texas Instruments |
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19 / 35 page ![]() 19 UCC24636 www.ti.com SLUSCG2A – MARCH 2016 – REVISED MARCH 2016 Product Folder Links: UCC24636 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 8.4 Device Functional Modes According to VDD voltage, VSC voltage, and VPC voltage and frequency, the device can operate in different modes. 8.4.1 Start-Up During start-up when VDD is less than VVDD(on) the device is disabled. When VDD exceeds the VVDD(on) UVLO threshold the IDD goes to IRUN and the device begins the start sequence detailed in Start Up and UVLO. 8.4.2 Normal Operation When VDD exceeds VVDD(on), the VPC voltage exceeds VVPC-EN and VVPC-TH, and the VSC voltage exceeds VVSCEN the DRV output is active. If the switching frequency is above the standby criteria of > 5 kHz the device is in normal operation determining the DRV time based on volt-sec control. IDD will be IRUN. 1. The device operates in volt-sec control based on the VPC and VSC volt-sec control ramps. 8.4.3 Standby Operation If the number of VPC pulses is less than nENTO, 64, during tENTO the device enters standby mode. DRV operation stops and most device functions are shut down. IDD is ISTBY during standby operation. To exit standby mode the number of VPC pulses must exceed nEN, 32, during tEN. IDD returns to IRUN and the DRV output starts after the initialization time as outlined in Figure 12. 8.4.4 Conditions to Stop Operation The following conditions can disable DRV operation; IDD is IRUN during these conditions. 1. VPC overvoltage: When VVPC > VVPCDIS for >500 ns the DRV output is disabled for the cycle. 2. VSC undervoltage: When VVSC < VVSCEN, the DRV output is disabled. 3. VPC undervoltage: When VVPC< VVPCEN, the DRV output is disabled. |
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