UCC24636DBVT datasheet(17/35 Pages) TI1

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tENTO

SR Driver Enabled

tEN

<64 cycles during tENTO

> 32 cycles

tEN

tENTO

SR Driver Disabled

Burst example

VPC Cycle Detect

Constant Fsw

VPC Cycle Detect

Burst Mode

SB Mode Enable

Fsw Averaging

Window

UCC24636

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SLUSCG2A – MARCH 2016 – REVISED MARCH 2016

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Feature Description (continued)

8.3.3 Standby Operation

To minimize power consumption at very light load and standby conditions, the UCC24636 disables the SR DRV

output and enters a low current operating state. The criteria for operating in standby mode or normal operation

are determined by the average frequency detected on the VPC pin. The frequency detection is compatible with

burst mode operation or continuous low frequency FM operation. At start up the device is in normal operation to

enable DRV to the SR MOSFET. If < 64 cycles occur in tENTO,12.8 ms typical, the device disables the DRV

output and enters low-current operating mode with bias current of ISTBY. In standby mode the criteria to enter

normal operating mode is when > 32 cycles occur within tEN, 2.56 ms typical. The device enters normal operation

as soon as the 32 cycles occur to reduce the response time exiting standby operation. The average frequency of

entering standby mode is 5 kHz typical, and the average frequency of exiting standby mode is 12.5 kHz typical.

Refer to Figure 17 for an illustration of standby mode timing.

Figure 17. Standby Mode Operation

UCC24636DBVT bảng dữ liệu(PDF) 17 Page - Texas Instruments