UCC24636DBVT datasheet(10/35 Pages) TI1

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VVDD

VVDD(on)

VTBLK

tINITIALIZE

20 µs

VVPC

VDRV

VPMOS

VDRCL

UCC24636

SLUSCG2A – MARCH 2016 – REVISED MARCH 2016

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8.3 Feature Description

8.3.1 Start Up and UVLO

The UCC24636 features a wide operating VDD range and low UVLO thresholds. The start up of the device is

dependent on voltage levels on three pins: VDD, VPC and VSC. The VDD pin can be directly connected to the

power supply output on converters from 5-V to 24-V nominal outputs. The start UVLO threshold is VVDD(on), 4.0 V

typical, and stop threshold is VVDD(off), 3.6 V typical. The DRV output is not enabled unless the voltage on the

VPC pin is greater than VVPCEN for a time longer than tVPC-BLK and the voltage on the VSC pin is greater than

VVSCEN. Once the VDD, VSC and VPC voltage and time thresholds are met, there is an internal initialization time

before the DRV output is enabled.

Refer to Figure 12 for a startup sequence that illustrates the timing sequence and configurable DRV output

based on VDD level. In most converter designs, the conditions for the VPC and VSC voltage to enable the

device are met before the VDD start-voltage threshold, this is reflected in the timing diagram. When VDD

exceeds VVDD(on) UVLO threshold the device starts the initialization sequence of 150 µs to 250 µs illustrated as

tINITIALIZE. After the device initialization, there is a logic initialization of 20 µs at which time VTBLK is enabled (high).

At VDD < VPMOS the driver high-side PMOS device is enabled and the DRV peak will be close to VDD. When

VDD exceeds VPMOS the PMOS device is disabled and the driver is operating as a high-side NMOS only and

DRV is approximately 1.2 V to 1.5 V lower than VDD. As VDD continues to increase, the DRV output is limited to

VDRCL regardless of VDD up to the recommended maximum rating.

Figure 12. Start-Up Operation

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