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MEC1322 bảng dữ liệu(PDF) 169 Page - Microchip Technology |
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MEC1322 bảng dữ liệu(HTML) 169 Page - Microchip Technology |
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169 / 456 page  2014 - 2015 Microchip Technology Inc. DS00001719D-page 169 MEC1322 12.12.3 SMI INTERRUPT SOURCE REGISTER 12.12.4 SMI INTERRUPT MASK REGISTER Offset 8h MBX_ INDEX 96h Bits Description Type Default Reset Event 7:1 EC_SWI EC Software Interrupt. An SIRQ to the Host is generated when any bit in this register when this bit is set to ‘1b’ and the corresponding bit in the SMI Interrupt Mask Register register is ‘1b’. This field is Read/Write when accessed by the EC at the EC offset. When written through the Host Access Port, each bit in this field is cleared when written with a ‘1b’. Writes of ‘0b’ have no effect. Host Access Port: R/WC EC: R/W 0h VCC1_R ESET 0EC_WR EC Mailbox Write. This bit is set automatically when the EC-to-Host Mailbox Register has been written. An SMI or SIRQ to the Host is generated when n this bit is ‘1b’ and the corresponding bit in the SMI Interrupt Mask Register register is ‘1b’. This bit is automatically cleared by a read of the EC-to-Host Mailbox Register through the Host Access Port. This bit is read-only when read through the Host Access Port. It is neither readable nor writable directly by the EC when accessed at the EC offset. Host Access Port: R EC: - 0h VCC1_R ESET Offset Ch MBX_ INDEX 97h Bits Description Type Default Reset Event 7:1 EC_SWI_EN EC Software Interrupt Enable. If this bit is ‘1b’, the bit EC_WR in the SMI Interrupt Source Register is enabled for the generation of SIRQ or nSMI events. Host Access Port: R/W EC: R/W 0h VCC1_R ESET 0EC_WR_EN EC Mailbox Write.Interrupt Enable. Each bit in this field that is ‘1b’ enables the generation of SIRQ interrupts when the corresponding bit in the EC_SWI field in the SMI Interrupt Source Register is ‘1b’. Host Access Port: R/W EC: R/W 0h VCC1_R ESET |
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