MEC1322 datasheet(97/456 Pages) MICROCHIP

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DS00001719D-page 97

MEC1322

5.11.5

MCHP TEST REGISTER

5.11.6

MCHP TEST REGISTER

1:0 Clock_Control

This field controls when the host interface will permit the internal ring

oscillator to be shut down. The choices are as follows:

0h:

Reserved

1h:

The host interface will permit the internal clocks to be shut down

if the CLKRUN# signals “CLOCK STOP” and there are no pending

serial interrupt request or DMA requests from devices associated

with the device. The CLKRUN# signals “CLOCK STOP” by

CLKRUN# being high for 5 LPCCLK’s after the raising edge of

CLKRUN#

2h:

The host interface will permit the ring oscillator to be shut down

after the completion of every LPC transaction. This mode may cause

an increase in the time to respond to LPC transactions if the ring

oscillator is off when the LPC transaction is detected.

3h:

The ring oscillator is not permitted to shut down as long as the

host interface is active. When the ACTIVATE bit in the LPC Activate

shut down and the Clock_Control Field is ignored. The Clock_Con-

trol Field only effects the Host Interface when the ACTIVATE bit in

the LPC Activate Register is 1.

Although the Host Interface can permit the internal oscillator to shut

down, it cannot turn the oscillator on in response to an LPC transac-

tion that occurs while the oscillator is off. In order to restart the oscil-

lator in order to complete an LPC transaction, EC firmware must

enable a wake interrupt on the LPC LFRAME# input. See the Appli-

cation Note in Section 15.8.1, "WAKE Generation" for details.

R/W

VCC1_

RESET

Offset

14h

Bits

Description

Type

Default

Reset

Event

31:8 RESERVED

RES

7:0 MCHP Reserved

VCC1_R

ESET

Offset

18h

Bits

Description

Type

Default

Reset

Event

31:2 RESERVED

RES

1 MCHP Reserved

R/W

VCC1_R

ESET

0 MCHP Reserved

R/W

VCC1_R

ESET

Offset

10h

Bits

Description

Type

Default

Reset

Event

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