UPD78C18 datasheet(72/110 Pages) NEC

72 / 110 page

µPD78C17,78C18

RESET OPERATIONS

When RESET input becomes low, then system reset is activated to create the following status.

o INTERRUPT ENABLE F/F is reset and interrupt is disabled.

o All the interrupt mask registers are set (1) and interrupt is masked.

o An interrupt request flag is reset (0) and pended interrupt is eliminated.

o All PSWs are reset (0).

o 0000H is loaded into the program counter (PC).

o The MODE A, MODE B, MODE C, and MODE F registers are set to FFH and the bits (MM0, 1, and 2) of the

MODE CONTROL C and MEMORY MAPPING registers are respectively reset (0), then all the

ports (A, B, C, D, and F) become input port (high-impedance).

o All the test flags but SB flag are reset (0).

o A timer mode register is set to FFH, and TIMER F/F is reset.

o The mode register (ETMM, EOM) of a timer/event counter is reset (0).

o The serial mode high register (SMH) of serial interface is reset (0), while the serial mode low register

(SML) is set to 48H.

o The A/D channel mode register of the A/D converter is reset (0).

o WR, RD, ALE signals become high-impedance.

o The ZC1, ZC2 bits of the zero-cross mode register (ZCM) are set (1).

o Data memory and the following register contents are undefined.

o The internal timing generator is initialized.

Stack pointer (SP)

Expansion accumulator (EA, EA’), accumulator (A, A’)

General register (B, C, D, E, H, L, B’, C’, D’, E’, H’, L’)

Output latch of each port

TIMER REG0, 1 (TM0, TM1)

TIMER/EVENT COUNTER REG0, 1 (ETM0, ETM1)

RAE bit of MEMORY MAPPING register

SB flag of test flag

When RESET input becomes high, the reset status is released. Then, execution of the program is started

from 0000H. The contents of various kinds of registers must be initialized or re-initialized in the program, if

necessary.

UPD78C18 bảng dữ liệu(PDF) 72 Page - NEC