UPD78C18 datasheet(49/110 Pages) NEC

49 / 110 page

µPD78C17,78C18

(4)

Serial mode register (SML, SMH)

These are two 8-bit registers which control the serial interface operation (see Figs. 2-28 and 2-29).

The serial mode low register (SML) bits 0 and 1 (B1, B2) control switchover of the asynchronous mode

and synchronous operation and clock rate in the asynchronous mode, bits 2 and 3 (L1, L2) control charac-

ter length, bit 4 (PEN) controls parity enable, bit 5 (EP) controls odd or even parity, and bits 6 and 7 (S1,

S2) control a number of stop bits.

After RESET input or in the hardware STOP mode, the serial mode low register (SML) is set to 48H.

The serial mode high register (SMH) bits 0 and 1 (SK1, SK2) control whether an internal clock or

external clock is used as the serial clock (SCK), bit 2 (TxE) controls the transmission operation, bit 3 (RxE)

controls the reception operation, bit 4 (SE) controls whether or not the search mode is set in the synchro-

nous mode. Bit 5 (IOE) controls whether the synchronous mode or I/O interface mode is set, and bit 6

(TSK) starts the serial clock when data is received using the internal clock in the I/O interface mode. The

TSK bit is automatically reset (0) after the serial clock starts.

When the serial clock is specified as an internal clock, the SCK value is determined by the following

expressions.

Internal clock (

φ24):

SCK = fXX/24

Internal clock (

φ384):

SCK = fXX/384

Internal clock (TO output):

Timer input clock is

φ12:

SCK = fXX/(24 x C)

Timer input clock is

φ384:

SCK = fXX/(768 x C)

TIMER F/F input is

φ3:

SCK = fXX/6

However, fXX is set in the oscillation frequency, SCK is set in the serial clock, and C is set in the timer

count value.

When TIMER F/F input is

φ3 in case of the internal clock (TO output), the asynchronous mode can only be

used when the clock rate is 16 or 64.

After RESET input or in the hardware STOP mode, the serial mode high register (SMH) is reset to 00H.

UPD78C18 bảng dữ liệu(PDF) 49 Page - NEC