UPD78C18 datasheet(47/110 Pages) NEC

47 / 110 page

µPD78C17,78C18

(3)

I/O interface mode

When input/output is extended to off-chip or I/O controllers (A/D converter, liquid crystal display

controller, etc.) are connected to this chip, this mode is effective.

In the I/O interface mode, data transfer is performed starting from the most significant bit (MSB) with

8-bit character length fixed, and with no parity bits. Therefore, the serial mode register (SML) should be

set to 0CH and bit 5 (IOE) of the serial mode register (SMH) is set to “1”.

This mode establishes synchronization by controlled SCK (8 cycles of the serial clock) and SCK should

be high except during data transfer.

The transmission operation is enabled by setting (1) bit 2 (TxE) of the serial mode register (SMH).

If data is written by the “MOV TXB, A” instruction, data is transferred to the serial register automati-

cally, and is output from TxD at the falling edge of controlled SCK. The transmit buffer is empty, the

internal interrupt (INTST) is generated.

Data transfer speed in transmission is maximum 500 kbps when an internal clock is used for SCK and

maximum 1 Mbps when an external clock is used (12-MHz operation).

The reception operation is enabled by setting (1) bit 3 (RxE) of the serial mode register (SMH), and

receive data is input to the serial register at the rising edge of controlled SCK. When the serial register

receives 8-bit data, data is transferred from the serial register to the receive buffer and the internal inter-

rupt (INTSR) is generated.

SCK can be selected as an internal clock or external clock by the serial mode register (SMH).

Data transfer speed in reception is maximum 500 kbps when an internal clock is used for SCK and

maximum 660 kbps when an external clock is used for SCK (12-MHz operation). 6 states or more is re-

quired in 8th SCK high-level width.

UPD78C18 bảng dữ liệu(PDF) 47 Page - NEC